CIS & CIR, EMC, and CU Boulder: Interconnection Scaling – Going Big and Going Small
Title: Interconnection Scaling – Going Big and Going Small
Abstract: This presentation will cover a high-level overview of interconnections between integrated circuits – trends over the past several decades and what technologies may support future trends, along with a discussion of basic signal integrity considerations for such interconnections. Over most of the past 50 years the scaling of silicon integration was the winning hand for increased performance with packaging and interconnections scaling at substantially lower rates. Fundamental challenges in nanometer process nodes have effectively ended the steadily increasing benefits of Moore’s Law so new paradigms for 2D, 2.5D, and 3D Heterogeneous Integration packaging technologies are being proposed and developed to keep system performance scaling moving forward. Rapidly moving a lot of data between chips is fundamental to all these approaches. One approach for dense, high bandwidth interconnections will be discussed in some detail to illustrate tradeoffs and discuss the limits of how interconnections between chips can reach the limits of interconnections within chips.
Date and Time
Location
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- Date: 13 Feb 2025
- Time: 06:30 PM to 08:00 PM
- All times are (UTC-07:00) Mountain Time (US & Canada)
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- 1111 Engineering Dr
- Boulder, Colorado
- United States 80309
- Building: Rustandy Building
- Room Number: KOBL 352
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- Co-sponsored by University of Colorado Boulder
- Starts 31 January 2025 12:00 AM
- Ends 13 February 2025 12:00 AM
- All times are (UTC-07:00) Mountain Time (US & Canada)
- 3 in-person spaces left!
- No Admission Charge
Speakers
Interconnection Scaling – Going Big and Going Small
Dr. Tim Michalka, PhD Electrical Engineer, Signal Integrity Expert Engineer
Biography:
Dr. Tim Michalka received a BS EE degree from the University of Maine in 1982 and MSEE & PhD EE degrees from Stanford University in 1983 and 1988. Dr. Tim Michalka has spent his career working on various aspects of electrical packaging and interconnections with an emphasis on signal and power integrity. Dr. Michalka’s industrial career beginning at Digital Equipment Corporation where he worked on electrical design aspects of IC packaging advanced development. Dr. Michalka worked at Carborundum Microelectronics he led the electrical analysis of aluminum nitride-based electronics packaging products. Then at Hewlett Packard he developed power integrity analysis methods for PA-RISC microprocessors and managed the electrical team overseeing package design and signal & power integrity analysis for server microprocessors and ASIC. Lastly Tim worked for Qualcomm where he founded and led Qualcomm’s primary signal and power integrity team which supported the development and production of the Qualcomm SOC chipset product portfolio. Tim retired from full-time work in 2022.
Agenda