Future III-V/CMOS Co-Integrated Technology and Hybrid Circuit Design
Abstract: As Moore’s Law is slowing down and eventually approaching an end for conventional CMOS, new platforms for producing circuit-level innovation are desired. At the same time, it is not desirable to throw away the existing Si-CMOS infrastructure to start new. The SMART-LEES (Singapore MIT Alliance for Research and Technology – Low Energy Electronic Systems) program is such a “vertical” innovative platform by “inserting” III-V layers into a conventional Si-CMOS foundry process. This talk presents an overview of the SMART-LEES program as well as a unified compact model for generic GaN/InGaAs-based HEMTs in the context of the hybrid III-V + CMOS technology being developed for future heterogeneous integrated circuits. The developed model has been implemented in a hybrid III-V/CMOS foundry PDK for designing heterogeneous circuits in III-V/Si co-integrated technology.
Date and Time
Location
Hosts
Registration
- Date: 22 Sep 2017
- Time: 01:40 PM to 02:40 PM
- All times are (UTC-06:00) Mountain Time (US & Canada)
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- University of Colorado at Colorado Springs
- 1420 Austin Bluffs Parkway
- Colorado Springs, Colorado
- United States 80918
- Building: ENG Building
- Room Number: 105
- Contact Event Host
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Dr. Kalkur's phone: (719) 255-3147
- Co-sponsored by Prof. T.S. Kalkur - Chair ECE Dept, UCCS
- Starts 11 September 2017 10:00 AM
- Ends 22 September 2017 11:00 AM
- All times are (UTC-06:00) Mountain Time (US & Canada)
- No Admission Charge
Speakers
Dr. Xing Zhou
Biography:
Dr. Xing Zhou obtained his B.E. degree in electrical engineering from Tsinghua University in 1983, M.S. and Ph.D. degrees in electrical engineering from the University of Rochester in 1987 and 1990, respectively. He has been with the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore since 1992. His past research interests include Monte Carlo simulation of photocarrier transport and ultrafast phenomena as well as mixed-mode circuit simulation and CAD tool development. His recent research mainly focuses on nanoscale CMOS compact model development. His research group has been developing a unified core model for nanoscale bulk, SOI, double-gate, nanowire CMOS, as well as III-V HEMTs. He has given more than 140 IEEE EDS distinguished lectures and invited talks at various universities as well as industry and research institutions. He is the founding chair for the Workshop on Compact Modeling (WCM) in association with the NSTI Nanotechnology Conference since 2002. Dr. Zhou was an editor for the IEEE Electron Device Letters during 2007–2016, a guest Editor-in-Chief for the special issue of the IEEE Transactions on Electron Devices (Feb. 2014) on compact modeling of emerging devices, and a member of the Modeling & Simulation subcommittee for IEDM (2016, 2017). He has been an EDS distinguished lecturer since 2000.
Email:
Address:School of Electrical and Electronic Engineering, Nanyuang Technological University, Singapore, Singapore, 639798
Dr. Xing Zhou
Biography:
Email:
Address:Singapore, Singapore