IEEE EPS Seminar: Progress and future of heterogenous system integration, packaging and reliability
Driving the success of European Semiconductor
Seminar overview
Heterogeneous system integration, packaging and reliability play a crucial role for the current and future development of semiconductors, quantum technologies and photonics. They are the key enabler to create new functionalities and business opportunities through the integration of different
types of cost-effective and high-performance chips, technologies and materials into a single system.
This seminar will discuss the progress and future challenges of heterogeneous integration, packaging, reliability and the potentials of creating more industry and business value.
Join us to explore the exciting opportunities that heterogeneous system integration can offer for the European ecosystem.
Date and Time
Location
Hosts
Registration
- Date: 10 Apr 2025
- Time: 06:00 AM UTC to 11:00 AM UTC
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- TU Delft
- Cornelis Drebbelweg
- Delft, Noord-Holland
- Netherlands 2628 CB
- Building: 36.HB.01.600
- Room Number: EEMCS-Lecture Hall Chip
- Contact Event Host
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This is an IEEE EPS Event at the TU Delft organized together with TU Delft (Prof. Kouchi Zhang) and IEEE EPS Benelux Section chapter (Rene Poelma)
- Co-sponsored by IEEE EPS Benelux Section Chapter
Speakers
Chris of Arizona State University, IEEE Fellow, chair of the IEEE EPS Phoenix Chapter
US Chips Act for Advanced Semiconductor Packaging and related programs at Arizona State University
Chris Bailey joined Arizona State University (ASU) in 2022 where he is Professor of Advanced Semiconductor Packaging. Prior to this he was Professor of Computational Mechanics & Reliability and Associate Dean for Research at the University of Greenwich, UK.. At ASU, Chris is leading on advanced semiconductor packaging, he is PI on an SRC funded project on Thermo-Mechanical Modelling and Reliability of Redistribution Layers, and Co-I on several large US-Chips-Act funded projects such as SWAP-Hub, SHIELD, and ITSI.
Chris has published 400+ archival papers in electronics packaging and received $40M+ from Government and Industry to support his research activities. Since 2010, Chris has served on the IEEE Electronics Packaging Society Board of Governors, and from 2020-2021, he was the President of the society. Recent awards include IEEE Electronics Packaging Society David Feldman Award and in 2024 he received the Societies Region 8 (Europe) award. He is chair of the EPS Phoenix Chapter, and co-chair for the Co-Design and Modelling & Simulation chapters for the Heterogeneous Integration Roadmap (HIR).
Gamal of SR Fellow AMD, IEEE Fellow, ASEM life Fellow, Member of National Academy of Engineering
Current and Future Challenges and Solutions in AI & HPC System and Thermal Management
Dr. Gamal Refai Ahmed is a highly respected technical executive with a distinguished career in thermal management, silicon architecture, and advanced packaging technologies. He has made substantial contributions to high-performance computing (HPC), artificial intelligence (AI), and microelectromechanical systems (MEMS). Dr. Refai Ahmed has held senior positions at leading companies including AMD, GE, Cisco, and Nortel. In his current role at AMD as Senior Fellow and Chief Architect, Dr. Refai- Ahmed has been pivotal in developing advanced silicon power thermomechanical architectures and enhancing hardware thermal management and packaging technologies for Xilinx products across various sectors, including telecom, data centers, and automotive.
Dr. Refai Ahmed’s achievements have been recognized with his election to the National Academy of Engineering and Fellowships with IEEE, ASME, and the Canadian Academy of Engineering. He has received the Presidential Medal from Binghamton State University, as well as the IEEE Canada R.H. Tanner Industrial Leadership Silver Medal Award. He has over 160 patents and `over 120 publications. He is also an IEEE Distinguished Lecturer.
Xuejun of Lamar University, IEEE Fellow, IEEE Distinguished Lecturer
Advanced Packaging Challenge for Chiplets and Heterogeneous Integration
Dr. Xuejun Fan is a Regents’ Professor of the Texas State University System and the Mary Ann and Lawrence E. Faust Endowed Professor at Lamar University, Beaumont, Texas. He is an IEEE Fellow, an IEEE Distinguished Lecturer, and serves as the co-chair of the Modeling and Simulation Committee for the Heterogeneous Integration Roadmap. Dr. Fan’s expertise lies in modeling, characterization, and reliability studies for heterogeneous integration. He has received several prestigious awards for his contributions to electronic packaging. His latest book, co-authored with Dr. John Lau, titled Hybrid Bonding, Advanced Substrates, Failure Mechanisms, and Thermal Management for Chiplets and Heterogeneous Integration, is set to be published in May 2025.
Mudasir of Google, manager of System Reliability & Adv. Numerical Analysis, IEEE Distinguished Lecturer
Multi-Physics Simulations: Accelerating Microelectronics Packaging for Artificial Intelligence Applications
Mudasir Ahmad is the group manager of the System Reliability and Adv. Numerical Analysis Team in the Global Hardware Quality and Reliability Organization in Google Technical Infrastructure. Before Google, he was a Distinguished Engineer/Senior Director at Cisco Systems, Inc. He has been involved with mechanical design, microelectronics packaging design and reliability analysis for more than 20 years, also in next generation 3D packaging, System-in-Package Modules, Chiplets and Silicon Photonics.
He is a Distinguished Lecturer of the IEEE EPS and participates in standards organizations and consortia such as IPC, JEDEC and ODSA. He was the chair of the local EPS chapter. He received the internationally Renowned Outstanding Young Engineer Award in 2012 from IEEE.
He received his M.S. in Management Science & Engineering at Stanford University, his M.S. degree in Mechanical Engineering from Georgia Tech and his B.S. from Ohio University. Mudasir has over 30 publications on microelectronic packaging, two book chapters, and 17 US Patents.
Saurabh of Senior Product Manager for Advanced Packaging market in business line DUV of ASML
Lithography Innovations for Artificial Intelligence
Saurabh Singh is Senior Product Manager for Advanced Packaging market in business line DUV of ASML, Netherlands. Over his 17 years ASML career he has held positions in Applications Engineering, Customer support, New product Introduction & Corporate Marketing. He has worked on wide variety of semiconductor applications of lithography from i-line to EUV. His current interest is next generation of advanced packaging & enabling these architectures by defining differentiated lithography solutions. He received his B Tech Electronics & Communication Engineering in India, and a MS in Photonics from Ghent University, Belgium
Agenda
Agenda:
08:30-08:50 - Welcome coffee
08:50-09:00 - Welcome speech
09:00-09:35 - Prof. Dr. Chris Bailey
09:35-10:10 - Dr. Gamal Refai-Ahmed
10:10-10:45 - Prof. Dr. Xuejun Fan
10:45-11:20 - Mudasir Ahmad
11:20-11:55 - Saurabh Singhir
IEEE EPS, Heterogenous Integration, Student Chapter, Workforce development
Media
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