DMEMS - PDH Series -"UNIVERSAL VERIFICATION METHOD: ASSURING DESIGN CORRECTNESS WITH CLASS"
UNIVERSAL VERIFICATION METHOD: ASSURING DESIGN CORRECTNESS WITH CLASS
UVM, a set of standardized prototype objects and classes to be used in SystemVerilog test benches, has become the industry standard tool for integrated circuit design verification. What is it, and what can it do for you?
This event is part of the IEEE San Diego Section's PDH series at the Del Mar Electronics and Manufacturing Show (Apr 23 - 24).
Date and Time
Location
Hosts
Registration
- Date: 24 Apr 2025
- Time: 05:00 PM UTC to 06:00 PM UTC
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- 2260 Jimmy Durante Blvd
- Del Mar Fairgrounds
- Del Mar, California
- United States 92014
- Building: Mission Tower
- Room Number: Room A
- Click here for Map
- Starts 24 March 2025 07:00 AM UTC
- Ends 24 April 2025 05:00 PM UTC
- Admission fee ?
Speakers
John A Eldon
Biography:
Dr. Eldon, a life senior member of IEEE and a member of the IEEE Consultants' Network, has designed and verified VLSI chips for various semiconductor companies since 1980, specializing in digital signal processing, imaging/video, and communications. He currently teaches VLSI design and verification courses at UC San Diego and consults in these fields. He holds three patents and developed numerous unpatented corporate trade secrets and has been a voting member of the IEEE 754 (floating point), ISO/IEC 14496 (MPEG-4), and IEEE 1800 (SystemVerilog) standards committees.
Email:
Address:United States
Agenda
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