IEEE Denver Dine & Learn: From Wafers to Cutting-Edge Products: The Process of Testing, Packaging, and Design

#Integrated #Circuits #Semiconductor #Manufacturing #Product #Design #Assembly #Testing #Packaging #Technology #Evolution
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Come join us for this Dine and Learn event hosted by the Denver Section and University of Colorado Boulder. You're invited to participate in an exciting and engaging presentation titled "From Wafers to Cutting-Edge Products: The process of Testing, Packaging, and Design" by Tim Swettlen.

Whether you're a college student eager to expand your knowledge or a technical professional looking to stay informed in this evolving industry, this presentation aims to cover the key test and assembly stages that deliver functional products to market.

* Food and beverage will be provided.

* Parking code will be provided to event registrants.

Abstract:

As Moore’s Law slows down on transistor density at the die level, advanced packaging methods are bridging the gap and continue to deliver ever more powerful products. To understand these changes, a thorough understanding of the testing flow is important as more die are stacked on a single final product.

This talk starts as the wafer exits the fab, is exposed to a battery of tests and routed to its highest value package and product. Each die on the wafer is processed on the same test flow but its testing results will direct it to different bins sold at different selling prices. These complex test flows allow the right parts to be assembled into the best final product whether it’s an advanced smart phone or an entry level AI accelerator card.



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  • Date: 18 Apr 2025
  • Time: 12:00 AM UTC to 02:00 AM UTC
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  • University of Colorado Boulder
  • 1095 Regent Drive
  • Boulder, Colorado
  • United States 80309
  • Building: Discovery Learning Center (DLC)
  • Room Number: 1B70

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  • Co-sponsored by University of Colorado Boulder
  • Starts 19 March 2025 06:00 AM UTC
  • Ends 18 April 2025 12:00 AM UTC
  • No Admission Charge


  Speakers

Tim Swettlen of University of Colorado Boulder

Biography:

Tim Swettlen graduated from Penn State University in 1996. Out of college he joined Intel working in the Test Development Organization. Over his first 10 years at Intel, Tim’s responsibilities expanded from wafer test support to leading small development teams responsible for the electrical integrity of test hardware.  

Over the next 12 years, Tim managed multiple engineering teams focused on all aspects of substrate package design, Printed Circuit Board (PCB) design, and high-volume readiness for PCB assembly and testing. Prior to leaving Intel, Tim managed an organization of 60 engineers responsible for designing packages for all of Intel’s client products; a 37 billion dollar a year business. The team was involved from platform development to customer designs.

After leaving Intel, Tim and his wife traveled the globe before relocating in Vietnam where they lived and worked for 3 years. During this period, Tim started his own consulting firm supporting clients in both Vietnam and in the US. Since moving back to the states in late 2023, Tim has been teaching PCB Design and Manufacturing at CU Boulder.  

Tim has 21 publications with 4 of these being awarded Best Paper, 8 patents issued, served on 3 industry conference technical committees, and has chaired the iNEMI PCB Technology Integration Group. 

Outside of work, Tim enjoys travel, running, and backpacking.





Agenda

Agenda:

6:00- 6:30PM    Food and networking

6:30-7:30 PM    Presentation

7:30- 8:00 PM   Q&A Discussion

8:00 PM             Adjourn