IEEE Circuit and System (CAS) Seasonal School on In-Memory Computing (IMC 2025) – (IMC 2024 Second Phase)
The main goal of this CAS seasonal school is to dive deep into the rapidly developing field of in-memory computing with a focus on Artificial intelligence (AI) and cover its cross-layer design challenges from device to algorithms. The IEEE Seasonal School in Circuits and Systems on In-Memory Computing (IMC 2025) offers talks and tutorials by leading researchers from multiple disciplines and prominent universities and promotes student short presentations to demonstrate new research and results, discuss the potential and challenges of the in-memory accelerators, future research needs, and directions, and shape collaborations.
First Talk Title (CAS DL Talk): Neuromorphic Computing: Bridging the gap between Nanoelectronics, Neuroscience and
Machine Learning
While research in designing AI algorithms has attained a stage where such platforms are able to outperform humans at several cognitive tasks, an often-unnoticed cost is the huge computational expenses required for running these algorithms in hardware. Recent explorations
have also revealed several algorithmic vulnerabilities of deep learning systems like adversarial susceptibility, lack of explainability, and catastrophic forgetting, to name a few. Brain-inspired neuromorphic computing has the potential to overcome these challenges of current AI systems. This talk reviews recent developments in the domain of neuromorphic computing from my group guided by an overarching system-science perspective with an end-to-end co-design focus from computational neuroscience and machine learning to hardware and applications. From the top-down algorithm side, I will delve into methodologies that treat neuromorphic spiking architectures as continuously evolving dynamical systems, revealing intriguing parallels with the learning dynamics in the brain. The methodologies discussed enable spiking architectures to transition beyond simple vision-related tasks to complex sequence learning problems and large language model (LLM) architectures. Complimentary to this effort, I will also elaborate on a bottom-up perspective of leveraging the intrinsic physics of emerging post-CMOS technologies like ferroelectrics and spintronics to mimic several neuro-synaptic functionalities in novel device structures operated at low terminal voltages. In-Memory computing architectures enabled by such neuromimetic devices have the potential of enabling two to three orders of magnitude energy efficiency in comparison to state-of-the-art CMOS implementations. I will outline several hardware-software co-design strategies to enable variation-aware, robust, self-healing neuromorphic systems. I will conclude my talk with my vision of expanding the scope of neuromorphic computing beyond simple neurons and synapses by forging stronger connections with computational neuroscience, thereby enabling a new generation of brain-inspired computers.
Second Talk Title: Towards AI-Native Hardware Design
In this talk, I will cover a body of work from NYU on democratizing and supercharging hardware design using modern AI/ML techniques, from design specification to logic synthesis and early-state timing and routing congestion prediction. I will begin by describing Verigen and CL-Verilog, the first specialized LLMs for automated Verilog code generation. To handle more complex designs, we will discuss our recent work on Chain-of-Thought approaches for hierarchical Verilog code generation and agentic frameworks to translate C code to HLS synthesizable C automatically. Next, I will discuss ABC-RL, a state-RL method to optimize logic synthesis, and VerilLoC, an early-stage predictive model to identify code blocks that can cause downstream timing closure issues. I will conclude by presenting my vision to build "end-to-end" foundation models for hardware design.
Date and Time
Location
Hosts
Registration
- Date: 10 Apr 2025
- Time: 12:30 PM UTC to 05:00 PM UTC
-
Add Event to Calendar
- 154 Summit Street, Newark, NJ 07102
- NJIT
- Newark, New Jersey
- United States 07102
- Building: ECEC Building
- Room Number: Eberhardt 112
- Click here for Map
- Contact Event Hosts
-
Dr. Ajay K. Poddar, Email:akpoddar@ieee.org
Dr. Durga Misra, Email: dmisra@ieee.org
Dr. Anisha M. Apte, Email: anisha_apte@ieee.org
- Co-sponsored by IEEE North Jersey Section
Speakers
Dr. Abhronil Sengupta of Penn State University
Neuromorphic Computing: Bridging the gap between Nanoelectronics, Neuroscience and Machine Learning
While research in designing AI algorithms has attained a stage where such platforms are able to outperform humans at several cognitive tasks, an often-unnoticed cost is the huge computational expenses required for running these algorithms in hardware. Recent explorations
have also revealed several algorithmic vulnerabilities of deep learning systems like adversarial susceptibility, lack of explainability, and catastrophic forgetting, to name a few. Brain-inspired neuromorphic computing has the potential to overcome these challenges of current AI systems. This talk reviews recent developments in the domain of neuromorphic computing from my group guided by an overarching system-science perspective with an end-to-end co-design focus from computational neuroscience and machine learning to hardware and applications. From the top-down algorithm side, I will delve into methodologies that treat neuromorphic spiking architectures as continuously evolving dynamical systems, revealing intriguing parallels with the learning dynamics in the brain. The methodologies discussed enable spiking architectures to transition beyond simple vision-related tasks to complex sequence learning problems and large language model (LLM) architectures. Complimentary to this effort, I will also elaborate on a bottom-up perspective of leveraging the intrinsic physics of emerging post-CMOS technologies like ferroelectrics and spintronics to mimic several neuro-synaptic functionalities in novel device structures operated at low terminal voltages. In-Memory computing architectures enabled by such neuromimetic devices have the potential of enabling two to three orders of magnitude energy efficiency in comparison to state-of-the-art CMOS implementations. I will outline several hardware-software co-design strategies to enable variation-aware, robust, self-healing neuromorphic systems. I will conclude my talk with my vision of expanding the scope of neuromorphic computing beyond simple neurons and synapses by forging stronger connections with computational neuroscience, thereby enabling a new generation of brain-inspired computers.
Biography:
: Dr. Abhronil Sengupta is an Associate Professor in the School of Electrical Engineering and Computer Science at Penn State University and holds the Joseph R. and Janice M. Monkowski Career Development Professorship. Dr. Sengupta received the PhD degree in Electrical and Computer Engineering from Purdue University in 2018 and the B.E. degree from Jadavpur University, India in 2013. He worked as a DAAD (German Academic Exchange Service) Fellow at the University of Hamburg, Germany in 2012, and as a graduate research intern at Intel Labs in 2016 and Meta Reality Labs in 2017. The ultimate goal of Dr. Sengupta’s research is to bridge the gap between Nanoelectronics, Neuroscience and Machine Learning. He is pursuing an inter-disciplinary research agenda at the intersection of hardware and software across the stack of sensors, devices, circuits, systems and algorithms for enabling low-power event-driven cognitive intelligence. Dr. Sengupta has published over 95 articles in referred journals and conferences and holds 3 US patents. He has been awarded the ARO Early Career Award (2024), Purdue Engineering 38 by 38 Award (2024), NSF CAREER Award (2023), IEEE Electron Devices Society (EDS) Early Career Award (2023), IEEE Circuits and Systems Society (CASS) Outstanding Young Author Award (2019), Meta Faculty Award (2018), IEEE SiPS Best Paper Award (2018), Schmidt Science Fellows Award nominee (2017), Purdue Bilsland Dissertation Fellowship (2017), CSPIN Student Presenter Award (2015), Birck Fellowship from Purdue University (2013), and the DAAD WISE Fellowship (2012). His work on neuromorphic computing has been highlighted in media by MIT Technology Review, ZDNet, US Department of Defense, American Institute of Physics, IEEE Spectrum, and Nature Materials, among others. Dr. Sengupta is a Senior Member of the IEEE and ACM. He currently serves as an ACM Distinguished Speaker (2024-2027) and IEEE CASS Distinguished Lecturer (2025-2026).
Email:
Address:State College , United States
Dr. Siddharth Garg of New York University
Towards AI-Native Hardware Design
In this talk, I will cover a body of work from NYU on democratizing and supercharging hardware design using modern AI/ML techniques, from design specification to logic synthesis and early-state timing and routing congestion prediction. I will begin by describing Verigen and CL-Verilog, the first specialized LLMs for automated Verilog code generation. To handle more complex designs, we will discuss our recent work on Chain-of-Thought approaches for hierarchical Verilog code generation and agentic frameworks to translate C code to HLS synthesizable C automatically. Next, I will discuss ABC-RL, a state-RL method to optimize logic synthesis, and VerilLoC, an early-stage predictive model to identify code blocks that can cause downstream timing closure issues. I will conclude by presenting my vision to build "end-to-end" foundation models for hardware design.
Biography:
Siddharth Garg is currently the Institute Associate Professor of ECE at NYU Tandon, where he leads the EnSuRe Research group (https://wp.nyu.edu/ensure_group/). He received his Ph.D. degree in Electrical and Computer Engineering from CMU in 2009, an MS in EE from Stanford, and a B.Tech. in EE from IIT Madras. In 2016, Siddharth was listed in Popular Science Magazine's annual list of "Brilliant 10" researchers. Siddharth has received the NSF CAREER Award, and paper awards at leading conferences including DATE, IEEE S&P and USENIX Security. Siddharth also received the Angel G. Jordan Award from ECE department of Carnegie Mellon University for outstanding thesis contributions and service to the community.
Email:
Address:New York University, , New York, United States
Agenda
Hybrid Event
Event Time: 8:30 AM to 1:00 PM
9:00-9:30 AM Registration and Networking
9:30-9:35 AM Opening Remarks by Dr. Shaahin Angizi, Vice-Chair, IEEE CAS/ED Chapter
9:35-9:40 AM Remark by Dr. Durga Misra, Chair, ECE Dept, NJIT and Chair, IEEE CAS/ED Chapter
9:40-10:00 AM Student Presentations (3-minute)
10:00-11:00 AM Talk I: Dr. Abhronil Sengupta (Penn State University)
Title: Neuromorphic Computing: Bridging the gap between Nanoelectronics, Neuroscience and Machine Learning
11:00 AM-12:00 PM Talk II: Dr. Siddharth Garg (New York University)
Title: Towards AI-Native Hardware Design
12:00 PM - 12:05 PM Concluding Remarks by Dr. Shaahin Angizi, Vice-Chair, IEEE CAS/ED Chapter
12:05 PM - 1:00 PM Lunch & Networking and Discussion
Location: Eberhardt Hall, Room 112, New Jersey Institute of Technology, Newark, NJ, USA
Online on Zoom, Link: https://njit-edu.zoom.us/j/
Meeting ID: 966 6486 5749
Passcode: 660738
All Welcome: There is no fee/charge for attending IEEE technical seminar. You don't have to be an IEEE Member to attend. Refreshments are free for all attendees. Please invite your friends and colleagues to take advantage of this Invited Distinguished Lecture.