Got a Lot of Chip Designin’ to Do
Chiplets are now the standard way to design chips at leading-edge nodes for applications such as AI and high-performance computing. Obvious challenges include the new stage of heterogeneous integration, the new bus that connects the chiplets, and the new advanced packages that hold it all together. No more afterthoughts; packaging, test, integration, and manufacturing must all start right with the design. And design teams and foundry teams must work closely together to achieve the best result. Power, thermal, and other analyses must evaluate both individual chiplets and the system-as-a-whole (including the package). The foundry will play a larger role than ever before because it will generally provide a choice of packages and perform the integration, and it will need fully tested (known good) dies to avoid wasting time and money on chips that fail inspection.
Date and Time
Location
Hosts
Registration
- Date: 02 May 2025
- Time: 01:30 AM UTC to 03:00 AM UTC
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- Santa Clara University
- Santa Clara, California
- United States
- Building: Heafey
- Room Number: 225
- Starts 27 March 2025 07:00 AM UTC
- Ends 02 May 2025 03:00 AM UTC
- Admission fee ?
- Menu: Regular Sandwich, Vegetarian Sandwich, Virtual, No Sandwich
Speakers
Jawad Nasrullah of Palo Alto Electron
Biography:
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Jawad Nasrullah is CEO of Palo Alto Electron, a startup focused on doing research on heterogeneous integrated circuits and developing 3D-ICs for performance computing. He was previously President, CTO, and Co-Founder of ZGlue, the creator of a platform for developing chiplets as well as a marketplace for distributing them. Before co-founding ZGlue, he was an engineer at Samsung Electronics, Intel, and Sun Microsystems. He earned a PhD in EE at Stanford, has 6 publications, and holds 14 patents. |