IC Chip and Packaging Interactions for Performance Improvements and Security Protections
Abstract:
Interactions of IC chips and packaging structures differentiate the electronic performance among traditional 2D chips and advanced 2.5D and 3D technologies. This presentation starts with their impacts on signal integrity (SI), power integrity (PI), electromagnetic compatibility (EMC) and electrostatic discharge protection (ESD), through indepth Si experiments with in-place noise measurements as well as full-chip and system level noise simulation. Additionally, the backside of an integrated circuit (IC) chip, more precisely, the backside surface of its Silicon substrate, provides open areas for circuit performance improvements and adversarial security attacks, that are potentially contradictory or traded off in design for performance and security. The talk also explores the security threats over the Si-substrate backside from both passive and active side-channel attack viewpoints and then discusses countermeasure principles.
Biography:
Makoto Nagata (Senior Member, IEEE) received the B.S. and M.S. degrees in physics from Gakushuin University, Tokyo, Japan, in 1991 and 1993, respectively, and the Ph.D. degree in electronics engineering from Hiroshima University, Hiroshima, Japan, in 2001. He was a Research Associate at Hiroshima University from 1994 to 2002, an Associate Professor at Kobe University, Kobe, Japan, from 2002 to 2009, where he was promoted to a Full Professor in 2009. His research interests include design techniques targeting high-performance mixed analog, RF and digital VLSI systems with particular emphasis on power/signal/substrate integrity and electromagnetic compatibility, testing and diagnosis, 2.5D and 3D system
integration, as well as their applications for hardware security and hardware safety, and cryogenic electronics for quantum computing. Dr. Nagata is a Senior Member of IEICE. He has been a member of a variety of technical program committees of international conferences, such as the Symposium on VLSI Circuits (2002–2009), Custom Integrated Circuits Conference (2007–2009), Asian Solid-State Circuits Conference (2005–2009), International Solid-State Circuits Conference (2014-2022), European Solid- State Circuits Conference (since 2020), and many others. He chaired the Technology Directions subcommittee for International Solid-State Circuits Conference (2018-2022) and served for an Executive Committee Member (2023-present). He was the Technical Program Chair (2010–2011), the Symposium Chair (2012–2013), and an Executive Committee Member (2014–2015) for the Symposium on VLSI circuits. He was the IEEE Solid-State Circuits Society (SSCS) AdCom member (2020-2022), the distinguished lecturer (2020-2021, and 2024-present), and currently serves as the chapters vice chair (2022-) of the society. He is an associate editor for IEEE Transactions on VLSI Systems (since 2015).
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- NTU,No. 1, Sec. 4, Roosevelt Rd.
- taipei, T'ai-pei
- Taiwan
- Building: Electrical Engineering 2
- Room Number: 124
- Click here for Map
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- Co-sponsored by SSCS Taipei Chapter
- Starts 09 April 2025 04:00 AM UTC
- Ends 23 April 2025 04:00 PM UTC
- No Admission Charge
