Dr. Mario Lanza of Department of Materials Science and Engineering, National University of Singapore, Singapore

Hardware implementations of artificial neural networks (ANNs)—the most advanced of which are made of millions of electronic neurons interconnected by hundreds of millions of electronic synapses—have achieved higher energy efficiency than classical computers in some small-scale data-intensive computing tasks. State-of-the-art neuromorphic computers, such as Intel’s Loihi or IBM’s NorthPole, implement ANNs using bio-inspired neuron- and synapse-mimicking circuits made of complementary metal–oxide–semiconductor (CMOS) transistors, at least 18 per neuron and six per synapse. Simplifying the structure and size of these two building blocks would enable the construction of more sophisticated, larger and more energy-efficient ANNs.

In this talk I will explain how a single CMOS transistor can exhibit neural and synaptic behaviours if it is biased in a specific (unconventional) manner. By connecting one additional CMOS transistor in series, we build a versatile 2-transistor-cell that exhibits adjustable neuro-synaptic response (which we named neuro-synaptic random access memory cell, or NS-RAM cell). This electronic performance comes with a yield of 100% and an ultra-low device-to-device variability, owing to the maturity of the silicon CMOS platform used—no materials or devices alien to the CMOS process are required. These results represent a short-term solution for the implementation of efficient ANNs and an opportunity in terms of CMOS circuit design and optimization for artificial intelligence applications. The MOSFET transistor keep surprising us and now—after this study—it seems to be the perfect building block for implementing ANNs.

Reference:

 Sebastian Pazos, Kaichen Zhu, Marco A. Villena, Osamah Alharbi, Wenwen Zheng, Yaqing Shen, Yue Yuan, Yue Ping, Mario Lanza*. Synaptic and neural behaviours in a standard silicon transistor. Nature 640, 69–76 (2025). https://doi.org/10.1038/s41586-025-08742-4

Biography:

Dr. Mario Lanza is an Associate Professor of Materials Science and Engineering at the National University of Singapore, since August 2024. He received his PhD in Electronic Engineering in 2010 at the Autonomous University of Barcelona, where he won the extraordinary PhD prize. In 2010-2011 he was NSFC postdoctoral fellow at Peking University, and in 2012-2013 he was Marie Curie postdoctoral fellow at Stanford University. On September 2013 he joined Soochow University (in China), where he was promoted to the rank of Full Professor. Between October 2020 and July 2024 he was full-time Associate Professor at the King Abdullah University of Science and Technology (in Saudi Arabia), where he became known for his work in the field of nano-electronics.

He has published over 200 research articles in top journals like Nature, Science and Nature Electronics, many of them becoming highly cited. He has been plenary, keynote, tutorial and invited speaker in over 150 conferences, and he and his students have received some of the most prestigious awards in the world (like the IEEE Fellow). He has been often consulted by leading semiconductor companies and publishers. He is an active member of the board governors of the IEEE – Electron Devices Society, and has been involved in the technical and management committee of top conferences in the field of electron devices, including IEDM, IRPS and IPFA. He speaks fluently five languages: English, Chinese, German, Spanish and Catalan.