DLP SSCS Vivienne Sze - Efficient Computing for AI and Robotics: From Hardware Accelerators to Algorithm Design
Lecture announcement
The IEEE Spain Chapter CASS-SSCS is pleased to announce the talk “Efficient Computing for AI and Robotics: From Hardware Accelerators to Algorithm Design” that will take place next July 14th at 11am in the Campus Nord of the Universitat Politècnica de Catalunya. This talk is sponsored by the IEEE Solid-State Circuits Society Distinguished Lecturer Program.
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- jordi Girona, 1-3
- Campus Nord UPC
- Barcelona, Cataluna
- Spain 08034
- Building: Edifici B3
- Room Number: Aula de Teleensenyament
- Click here for Map
Speakers
Vivienne Sze of MIT
Efficient Computing for AI and Robotics: From Hardware Accelerators to Algorithm Design
The compute demands of AI and robotics continue to rise due to the rapidly growing volume of data to be processed; the increasingly complex algorithms for higher quality of results; and the demands for energy efficiency and real-time performance. In this talk, we will discuss the design of efficient hardware accelerators and the co-design of algorithms and hardware that reduce the energy consumption while delivering real-time and robust performance for applications including deep neural networks, data analytics with sparse tensor algebra, and autonomous navigation. We will also discuss our recent work that balances flexibility and efficiency for domain-specific accelerators and reduce the cost of analog-to-digital converters for processing-in-memory accelerators. Throughout the talk, we will highlight important design principles, methodologies, and tools that can facilitate an effective design process.
Biography:
Vivienne Sze is an Associate Professor in the Electrical Engineering and Computer Science Department at MIT. She works on computing systems that enable energy-efficient machine learning, computer vision, and video compression/processing for a wide range of applications, including autonomous navigation, digital health, and the internet of things. She is widely recognized for her leading work in these areas and has received awards, including faculty awards from Google, Facebook, and Qualcomm, the Symposium on VLSI Circuits Best Student Paper Award, the IEEE Custom Integrated Circuits Conference Outstanding Invited Paper Award, and the IEEE Micro Top Picks Award. As a member of the Joint Collaborative Team on Video Coding, she received the Primetime Engineering Emmy Award for the development of the High-Efficiency Video Coding video compression standard. She is a co-editor of High Efficiency Video Coding (HEVC): Algorithms and Architectures (Springer, 2014) and co-author of Efficient Processing of Deep Neural Networks (Synthesis Lectures on Computer Architecture, Morgan Claypool, 2020). For more information about Prof. Sze’s research, please visit: http://sze.mit.edu