Design of Discrete-Time Receivers for the Internet-of-Things
#IoT
#Receiver
#Analog
#Electronics
Internet-of-Things (IoT) imposes severe requirements on ultra-low power consumption of radio frequency transceivers. Battery life is critical in these applications and can be extended by lowering supply voltage to reduce power consumption. In the receiver part of the radio, the analog front-end section is the most power-hungry subsystem and has received a lot of attention lately, mainly from the analog continuous-time point of view. Advances in discrete-time receiver designs, however, offer new alternatives with simpler and technology-scalable switched-capacitor circuits and easy calibration of intermediate frequency and band-pass selection based on capacitor ratios, which are less sensitive to process variations. New passive charge-domain switched-capacitor filter topologies and accurate control of sampling rates, both of which benefit from technology scaling and enable easier-to-design low-power solutions, have been introduced. Another important aspect of the proposed low-power solution is full integration of all the RF building blocks to reduce system costs. These new band-pass filters are highly selective and enable saw-less solutions for either low-power or high-performance applications. The super-heterodyne receiver is the architecture of choice with less issues regarding flicker noise, second-order linearity and time-varying DC offsets, besides not requiring the bulky external filters used in the past. This tutorial presents the recently developed concepts in discrete-time receivers leading to an ultra-low-power state-of-the-art Bluetooth Low Energy receiver which was implemented in low cost TSMC 28 nm bulk CMOS.
Date and Time
Location
Hosts
Registration
- Date: 18 Dec 2017
- Time: 12:30 PM to 02:00 PM
- All times are (UTC+01:00) Warsaw
-
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- AGH University of Science and Technology
- Cracow, Malopolskie
- Poland 30-059
- Building: B4
- Room Number: H-113
Speakers
Robert Bogdan Staszewski, Prof. of University College Dublin
Topic:
Design of Discrete-Time Receivers for the Internet-of-Things
Biography:
- Bogdan Staszewski received BSEE (summa cum laude), MSEE and PhD from University of Texas at Dallas, USA, in 1991, 1992 and 2002, respectively. From 1991 to 1995 he was with Alcatel in Richardson, Texas. He joined Texas Instruments in Dallas, Texas in 1995. In 1999 he co-started a Digital RF Processor (DRP) group in TI with a mission to invent new digitally intensive approaches to traditional RF functions. Dr. Staszewski served as a CTO of the DRP group between 2007 and 2009. In July 2009 he joined Delft University of Technology in the Netherlands where he is currently a part-time Full Professor. Since Sept. 2014 he is a Full Professor at University College Dublin (UCD) in Ireland. He has co-authored two books, four book chapters, 230 journal and conference publications, and holds 160 issued US patents. His research interests include nanoscale CMOS architectures and circuits for frequency synthesizers, transmitters and receivers. He is an IEEE Fellow and a recipient of IEEE Circuits and Systems Industrial Pioneer Award (http://ieee-cas.org/about/awards/industrial-pioneer-award).
Email:
Address:School of Electrical & Electronic Engineering, Room 243, UCD Engineering & Materials Science Centre, Dublin, Ireland
Robert Bogdan Staszewski, Prof. of University College Dublin
Topic:
Design of Discrete-Time Receivers for the Internet-of-Things
Biography:
Email:
Address:Dublin, Ireland
Agenda
12:30 - 14:00,
H-113, B4, AGH University of Science and Technology, Cracow, Poland