Distinguished Lecture: Alvin Loke – "The Road to Gate-All-Around and Its Impact on Analog Design"

#cmos-technology #mosfet #process-technology #IEEESSCSGermany #circuits

Despite the much debated end of Moore's Law, CMOS scaling still maintains economic relevance with 3nm finFET SoCs already in the marketplace for over a year and 2nm gate-all-around SoCs anticipated this year. Modest feature size reduction and design/technology innovations co-optimized for primarily logic scaling continue to offer compelling node-to-node power, performance, area, and cost benefits. In this tutorial, we will start with a walk through memory lane, recounting a brief history of transistor evolution to motivate the migration from the planar MOSFET to the fully depleted FinFET. We will summarize the key process technology elements that have enabled the finFET CMOS nodes, highlighting the resulting device technology characteristics and challenges. This will set the context for motivating the introduction of the gate-all-around transistor architecture, namely nanoribbons or nanosheets, and unveiling the magic of how these devices are fabricated. We will then shift to summarize the challenges that CMOS technology scaling has imposed on analog design. To address the growing effort required for analog/mixed-signal design closure, we will cover design strategies on how analog design has adapted and thrived throughout decades of increasingly unfriendly CMOS scaling, including the migration to heterogeneous integration as prophesied by Gordon Moore's seminal 1965 paper.

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• Schatzbogen 7
• Munich, Bayern
• Germany 81829
• Building: NXP Semiconductors Germany GmbH
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• Co-sponsored by NXP Semiconductors

• Starts 21 July 2025 10:00 PM UTC
• Ends 04 September 2025 02:00 PM UTC
• No Admission Charge

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