1st International Conference on Electronics & Packaging Technologies (EPTC 2026)
IEEE EPT Conference 206 is an international conference organized by the IEEE EPS Delhi Chapter and co-sponsored by the IEEE Electronics Packaging Society (EPS) along with Manav Rachna International Institute of Research & Studies.
Set in the backdrop of a verdant, green campus in the Aravalli hills, the event is hosted at Manav Rachana International Institute of Research & Studies, Faridabad, Delhi-NCR. It will feature keynotes, tutorials, technical sessions, invited talks, panels, workshops, exhibitions, and networking activities.
Topics include modules, components, materials, equipment technology, assembly, reliability, interconnect design, device and systems packaging, heterogeneous integration, wafer-level packaging, flexible electronics, LED, IoT, 5G, emerging technologies, 2.5D/3D integration technology, smart manufacturing, automation, and AI. Planned in tandem with the Gujarat Semiconnect (SMarch 5-6, 2026 ), the event is expected to pull in ~250 academia/industry participants.
Date and Time
Location
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- Manav Rachna International Institute of Research & Studies
- Suraj Kund Badkhal Road, Sector 43
- Faridabad, Haryana
- India 121004
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- Co-sponsored by Manav Rachna International Institute of Research & Studies, Faridabad
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- Starts 27 July 2025 06:30 PM UTC
- Ends 01 March 2026 06:30 PM UTC
- No Admission Charge
Speakers
Dr Ashwini of Ashwini Kumar Aggarwal
Bridging Skills & Innovation for India's Semiconductor Industry
India is at a pivotal juncture in its semiconductor journey, with strong national momentum toward self-reliance and global competitiveness. Realizing this vision requires a robust talent ecosystem aligned with industry needs and emerging technologies.
This presentation highlights the strategic framework for building semiconductor manufacturing skills in India, anchored by the nationally approved curriculum developed under the leadership of the Semiconductor Manufacturing Skill Committee at ESSCI. As co-authored by domain experts and integrated into AICTE programs, the curriculum represents a milestone in standardizing and scaling workforce development across academia and industry.
The session will explore key innovations in curriculum design, implementation strategies, and capacity-building efforts, including nationwide faculty training and industry-aligned workshops. It will also outline a roadmap for fostering an innovation-driven talent pipeline capable of powering India's semiconductor ambitions.
Biography:
Dr.Ashwini Aggarwal is the chair of EPTC India and the Professor of Practice at Manav Rachna International Institute for Research Studies at Faridabad/Delhi NCR, an IEEE Senior Member, Founder Chair of the Delhi NCR Chapter of IEEE EPS (semiconductor packaging) & a member of IEEE Delhi Executive Committee. He is a Fellow of the Institute of Electronics and Telecom Engineers.
Dr Ashwini has over 40+ years of industry experience, has retired from Applied Materials (US MNC) in August'24. He is a consultant to Organization for Economic Cooperation and Development and to global MNC clients in the semiconductor/display/nano-technology space in his professional practise. He is also the chair of the semiconductor manufacturing NOS ( skill) committee at Electroniics Sector Skill Council and has contributed to the AICTE revised curriculum on the subject as a part of the advisory committee for semiconductor and VLSI stream.
Email:
Address:541 Sector 9, Faridabad - 121006, Faridabad, Haryana, India, 121006
Dr Umesh of MRIE
Biography:
Dr Umesh Dutta is the co-chair of EPTC India - and the CEO of Manav Rachna Innovation and Incubation Foundation at Manav Rachna Education Institutes. He is also the Vice Chair of the IEEE EPS Delhi Chapter.
Email:
Address:Manav Rachna Innovation & Incubation Foundation, Sector 43 Suraj kund Road, Faridabad, Haryana, India, 121004
Agenda
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