VLSI Workshop 2 by Synopsys
The VLSI Workshop II, conducted by Synopsys, is designed to provide participants with hands-on experience in industry-standard Electronic Design Automation (EDA) tools used in power and timing analysis workflows. The workshop covers PrimePower for detailed gate-level power analysis, PrimePower RTL for early-stage power estimation, and PrimeTime for comprehensive static timing analysis. These sessions will help participants develop a strong understanding of essential methodologies applied in real-world VLSI design environments.
This workshop is ideal for undergraduates passionate about VLSI and digital system design, offering them exposure to advanced tools widely used in the semiconductor industry. By engaging in practical exercises and guided analysis, participants will gain valuable insights into optimizing designs for power efficiency and timing accuracy. With a focus on bridging academic concepts with professional applications, the workshop provides an excellent opportunity to enhance both technical knowledge and practical skills in modern chip design workflows.
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- Faculty of Engineering
- University of Peradeniya
- Peradeniya, Sri Lanka
- Sri Lanka 20400
- Building: Computer Lab 02
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- Co-sponsored by Synopsys Lanka (Pvt) Ltd