Emulation and Verification of Digital Designs
There will be a presentation providing an overview of the main design verification methods for digital ASICs, within the context of a complete development roadmap. The focus will be on the emulation technique, highlighting its particularities and how it differs from other approaches such as simulation, prototyping, and formal verification.
Short Bio: Guilherme Resende Vieira holds a Bachelor's degree in Computer Science from the Federal University of Minas Gerais (UFMG), with 7 years of experience as a Design Verification Engineer at Cadence Design Systems. He is currently working as a Lead Design Engineer, focusing on digital ASIC projects for Emulation.
Date and Time
Location
Hosts
Registration
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- Av. Pres. Antônio Carlos, 6627
- 80
- Belo Horizonte, Minas Gerais
- Brazil 31330-670
- Building: School of Engineering
- Room Number: O ChatGPT disse: Seminar Room 1020
Speakers
Guilherme of UFMG
Short Bio: Guilherme Resende Vieira holds a Bachelor's degree in Computer Science from the Federal University of Minas Gerais (UFMG), with 7 years of experience as a Design Verification Engineer at Cadence Design Systems. He is currently working as a Lead Design Engineer, focusing on digital ASIC projects for Emulation.
Biography:
Short Bio: Guilherme Resende Vieira holds a Bachelor's degree in Computer Science from the Federal University of Minas Gerais (UFMG), with 7 years of experience as a Design Verification Engineer at Cadence Design Systems. He is currently working as a Lead Design Engineer, focusing on digital ASIC projects for Emulation.
Address:Belo Horizonte, Minas Gerais, Brazil, 31330-670
Agenda
August 14, 2025, at 1:30 PM
Seminar Room 1012 – School of Engineering – Federal University of Minas Gerais