NAND Flash Memory: Scaling Challenges for the Next-Gen AI Applications
Since its inception in late 1980s, innovations in NAND flash have enabled massive growth in bit density along with better performance and significant cost reduction. This has made NAND Flash the choice of storage media as the Artificial Intelligence (AI) models continue to grow. As the AI era applications expand in scope, NAND FLASH faces new market opportunities and scaling challenges. Due to the demand for efficient and high-performance memory solutions, the push to keep NAND on a sustainable scaling path has never been stronger. This talk will review technology advances in material, process, device and design that have fueled the NAND scaling in 2D as well as 3D era. Several technology proposals to overcome the cost-performance trade-off of layer stacking are covered that will pave the path for continue cell scaling with gate all around (GAA) architecture.
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- Ingram School of Engineering
- 327 W Woods Street
- San Marcos, Texas
- United States 78666
- Building: INGR
- Room Number: INGRAM ROOM 3207
- Contact Event Host
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Dr. Ariful Haque, Assistant Professor of EE, ISoE, Texas
State University, ahaque@txstate.edu - Co-sponsored by Electronic Materials Committee - IEEE Electron Devices Society
- Starts 08 September 2025 05:00 AM UTC
- Ends 11 September 2025 06:00 PM UTC
- No Admission Charge
Speakers
Dr. Shyam Surthi
NAND Flash Memory: Scaling Challenges for the Next-Gen AI Applications
Since its inception in late 1980s, innovations in NAND flash have enabled massive growth in bit density along with better performance and significant cost reduction. This has made NAND Flash the choice of storage media as the Artificial Intelligence (AI) models continue to grow. As the AI era applications expand in scope, NAND FLASH faces new market opportunities and scaling challenges. Due to the demand for efficient and high-performance memory solutions, the push to keep NAND on a sustainable scaling path has never been stronger. This talk will review technology advances in material, process, device and design that have fueled the NAND scaling in 2D as well as 3D era. Several technology proposals to overcome the cost-performance trade-off of layer stacking are covered that will pave the path for continue cell scaling with gate all around (GAA) architecture.
Biography:
Biography: Shyam Surthi is currently Distinguished Member of Technical Staff in Advanced NAND Technology team at Micron Technology Inc. He received BS and MS in Chemical Engineering from the University Institute of Chemical Technology (Mumbai, India) and Ph.D. in electrical engineering from the University of Alabama, specializing in processing and characterization of Perovskite materials. Subsequently, he was a Postdoctoral Fellow at North Carolina State University developing Si-molecular devices for memory applications. Shyam joined Diffusion Process development at Micron in 2004, working on various films development projects and later transitioning to Advanced DRAM Process Integration role. Since 2011, Shyam has been in various people leadership roles in films process development for DRAM and emerging memory and technical leadership roles in NAND pathfinding with focus on integration. Shyam is a Senior Member of IEEE and holds 72 U.S. patents and several international patents. He has 25 publications in refereed technical journals and conference proceedings.