Makoto Ikeda of SSCS DL

This lecture will overlook basics and variety of asynchronous controlling, from the view point of advantages for low-voltage & variation rich conditions. This lecture takes two extreme example of complete completion detection type asynchronous designs as examples and demonstrate details of operation and performance. In addition, this talk will cover recent trial on design flow of random logic by the self-synchronous circuits.

Biography:

Makoto Ikeda received the BE, ME, and Ph.D. degrees in electrical engineering from the University of Tokyo, Tokyo, Japan, in 1991, 1993 and 1996, respectively. He joined the University of Tokyo as a research associate, in 1996, and now professor and director of Systems Design Lab(d.lab), the University of Tokyo. At the same time he has been involving the activities of VDEC(VLSI Design and Education Center, the University of Tokyo), to promote VLSI design educations and researches in Japanese academia. He worked for hardware security, asynchronous circuits design, smart image sensor for 3-D range finding, and time-domain signal processing. He has been serving various positions of various international conferences, including ISSCC ITPC Chair(ISSCC 2021), IMMD sub-committee chair (ISSCC 2015-2018), A-SSCC 2015 TPC Chair, VLSI Circuits Symposium PC Chair(2017)&Symposium Chair(2019). He is a senior member of IEEE, IEICE Japan, and a member of IPSJ and ACM.

Email:

Address:Tokio, Tokyo, Japan