Challenges and opportunities for ultra-low power design for quantum computing applications

#quantum-computing #frequency #technology #power-dissipation #cmos #bandwidth

This talk will cover practical challenges for cryogenic CMOS designs for next
generation quantum computing. Starting from system level, it will detail the design considerations
for a non-multiplexed, semi-autonomous, transmon qubit state controller (QSC) implemented in
14nm CMOS FinFET technology. The QSC includes an augmented general-purpose digital
processor that supports waveform generation and phase rotation operations combined with a low
power current-mode single sideband upconversion I/Q mixer-based RF arbitrary waveform
generator (AWG). Implemented in 14nm CMOS FinFET technology, the QSC generates control
signals in its target 4.5GHz to 5.5 GHz frequency range, achieving an SFDR > 50dB for a signal
bandwidth of 500MHz. With the controller operating in the 4K stage of a cryostat and connected
to a transmon qubit in the cryostat’s millikelvin stage, measured transmon T1 and T2 coherence
times were 75.5μS and 73 μS, respectively, in each case comparable to results achieved using
conventional room temperature controls. In further tests with transmons, a qubit-limited error rate
of 7.76x10-4 per Clifford gate is achieved, again comparable to results achieved using room
temperature controls. The QSC’s maximum RF output power is -18 dBm, and power dissipation
per qubit under active control is 23mW. An improved, low power design version using end to end
current mode design that achieves half of this power will also be presented to demonstrate ultra-
low power scaling using current mode techniques.

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• Engineering and Science Building (ESB), American University of Sharjah (AUS)
• Sharjah, United Arab Emirates
• United Arab Emirates
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