Co-Packaged Optics – 3D Heterogeneous Integration of Photonic IC and Electronic IC
Technical seminar by IEEE Electronics Packaging Society Distinguished Lecturer Dr. John H. Lau with the following abstract:
Silicon photonics are the semiconductor integration of EIC and PIC on a silicon substrate (wafer) with complementary metal-oxide semiconductor (CMOS) technology. On the other hand, co-packaged optics (CPO) are heterogeneous integration packaging methods to integrate the optical engine (OE) which consists of photonic ICs (PIC) and the electrical engine (EE) which consists of the electronic ICs (EIC) as well as the switch ASIC (application specific IC). The advantages of CPO are: (a) to reduce the length of the electrical interface between the OE/EE (or PIC/EIC) and the ASIC, (b) to reduce the energy required to drive the signal, and (c) to cut the latency which leads to better electrical performance. In the next few years, we will see more implementations of a higher level of heterogeneous integration of PIC and EIC, whether it is for performance, form factor, power consumption or cost. The content of this lecture is shown below.
- Silicon Photonics
- Data Centers
- Optical Transceivers
- Optical Engine (OE) and Electrical Engine (EE)
- OBO (on-board optics)
- NPO (near-board optics)
- CPO (co-packaged optics)
- 3D Integration of the PIC and EIC
- 3D Heterogeneous Integration of PIC and EIC
- 3D Heterogeneous Integration of ASIC Switch, PIC and EIC
- 3D Heterogeneous Integration of ASIC Switch, PIC and EIC with Bridges
- 3D Heterogeneous Integration of ASIC Switch, EIC and PIC embedded in Glass-core Substrate
- Summary and Recommendations
Date and Time
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- 2356 Main Mall
- Vancouver, British Columbia
- Canada V6T 1Z4
- Building: MacLeod Building
- Room Number: MCLD 3038
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sudip@ece.ubc.ca
- Starts 08 October 2025 07:00 AM UTC
- Ends 17 October 2025 07:00 PM UTC
- No Admission Charge
Speakers
John Lau of Unimicron Technology Corporation
Co-Packaged Optics – 3D Heterogeneous Integration of Photonic IC and Electronic IC
Technical seminar by IEEE Electronics Packaging Society Distinguished Lecturer Dr. John H. Lau with the following abstract:
Silicon photonics are the semiconductor integration of EIC and PIC on a silicon substrate (wafer) with complementary metal-oxide semiconductor (CMOS) technology. On the other hand, co-packaged optics (CPO) are heterogeneous integration packaging methods to integrate the optical engine (OE) which consists of photonic ICs (PIC) and the electrical engine (EE) which consists of the electronic ICs (EIC) as well as the switch ASIC (application specific IC). The advantages of CPO are: (a) to reduce the length of the electrical interface between the OE/EE (or PIC/EIC) and the ASIC, (b) to reduce the energy required to drive the signal, and (c) to cut the latency which leads to better electrical performance. In the next few years, we will see more implementations of a higher level of heterogeneous integration of PIC and EIC, whether it is for performance, form factor, power consumption or cost. The content of this lecture is shown below.
- Silicon Photonics
- Data Centers
- Optical Transceivers
- Optical Engine (OE) and Electrical Engine (EE)
- OBO (on-board optics)
- NPO (near-board optics)
- CPO (co-packaged optics)
- 3D Integration of the PIC and EIC
- 3D Heterogeneous Integration of PIC and EIC
- 3D Heterogeneous Integration of ASIC Switch, PIC and EIC
- 3D Heterogeneous Integration of ASIC Switch, PIC and EIC with Bridges
- 3D Heterogeneous Integration of ASIC Switch, EIC and PIC embedded in Glass-core Substrate
- Summary and Recommendations
Biography:
John H. Lau (Life Fellow, IEEE) received the Ph.D. degree from the University of Illinois at Urbana–Champaign in 1977 and three master degrees from the University of British Columbia in 1973, the University of Wisconsin–Madison in 1974, and Fairleigh Dickinson University in 1979. He also earned a bachelor’s degree from the National Taiwan University in 1970. He was a Senior Scientist/MTS with the Hewlett-Packard Laboratory and Agilent, Palo Alto, CA, USA, for 20 years, the Director of the System Packaging Laboratory, Institute of Microelectronics, Singapore, for two years, a Visiting Professor with The Hong Kong University of Science and Technology, Hong Kong, for one year, a Specialist with the Industrial Technology Research Institute, Taiwan, for five years, and a Senior Technical Advisor with ASM Pacific Technology, Hong Kong, for five years. He was the CTO from July 2019 to June 2021 and has been a Senior Special Project Assistant with Unimicron Technology Corporation, Taiwan, since July 2021. He has more than 40 years of research and development and manufacturing experiences in semiconductor packaging and surface-mount technology assembly, published more than 530 peer-reviewed papers (385 are the principal investigator), 52 issued and pending U.S. patents (31 are the principal inventor), and 23 textbooks such as Chiplet Design and Heterogeneous Integration Packaging (Springer, 2023) and Flip Chip, Hybrid Bonding, Fan-in and Fan-out Technology (Springer, 2024). John is an elected ASME Fellow and IMAPS Fellow and has been actively participating in industry/academy/society meetings/conferences to contribute, learn, and share. He received many awards, including the ASME Worcester Reed Warner Medal and the IEEE Components Packaging and Manufacturing Technology Field Award.
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