3D heterogeneous integration: 2.5D and 3D integration landscape and roadmap, opportunities for power conversion
This talk presents an overview of the evolving landscape and roadmap of 2.5D and 3D heterogeneous integration technologies, which are reshaping the future of semiconductor design and system architecture. As device scaling approaches its physical and economic limits, advanced packaging and vertical integration have emerged as key enablers for achieving higher performance, energy efficiency, and functional density.
The presentation will first review the current state of 2.5D and 3D integration, including silicon interposers, through-silicon vias (TSVs), hybrid bonding, and advanced chiplet-based architectures. These technologies enable the integration of logic, memory, analog, and power components within a single package, drastically reducing interconnect parasitics and improving bandwidth and power efficiency.
Particular emphasis will be placed on the emerging opportunities for power conversion within heterogeneous systems. With the increasing demand for high-current, low-voltage power delivery in AI, high-performance computing (HPC), and data center applications, 3D integration offers new design paradigms for embedding power management circuits closer to the load. This reduces power loss, improves transient response, and enhances overall system reliability.
The talk will conclude with a forward-looking roadmap highlighting research and industrial trends in 3D heterogeneous integration — including materials innovation, thermal management, design automation, and standardization efforts — and how these advancements open new pathways for energy-efficient, high-performance system design across next-generation electronic platforms.
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Geert Van der Plas
Biography:
Geert Van der Plas (Member, IEEE) received the Ph.D. degree from Katholieke Universiteit Leuven, Leuven, Belgium, in 2001.,He joined IMEC, Heverlee, Belgium, in 2003, working on energy-efficient data converters, power/signal integrity, and 3-D integration technologies, where he is currently the Program Manager in 3-D program addressing system scaling using advanced 3-D through-silicon via (TSV) and packaging fan-out wafer-level packaging (FO-WLP) technology for high-performance, mobile, and the Internet of Things (IoT) applications. His research interests are in characterization, modeling, system exploration, and design enablement of 3-D integration technologies.
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