Scalable Verification Framework for Complex System-on-Chip Designs

#WIE #HardwareEngineering #SystemOnChip #WomenInTech

The IEEE Women in Engineering New Zealand North Section invites you to a technical webinar with Ras Attale, a Senior Hardware Engineer at Siemens, with nearly seven years of experience on the team. Previously worked at Arm, contributing to their verification team in Cortex A. Also currently pursuing a Master’s in Cybersecurity at the University of Oxford.

The webinar will discuss a comprehensive framework for scalable verification of complex system-on-chip (SoC) designs. This solution addresses the growing challenges of verification complexity through reusable test plans that maximize component and protocol reusability across multiple IP blocks. The framework implements requirement-driven verification to ensure complete traceability between design requirements and the verification process. Real-time interactive dashboards with AI features deliver immediate visibility into verification progress, enabling early bug detection, optimized resource allocation, and data-driven decision making. The methodology employs systematic coverage collection and closure techniques, including a traffic light system for waivers, while emphasizing the importance of creating detailed verification test plans linked to design requirements from project inception. Through this Metric Driven Verification approach, the Tessent Embedded Analytics verification flow helps engineering teams manage complex verification environments more efficiently.