Tae of Cisco

Sn-based solder joints have quietly moved along with the progress of electronic packaging, reliably bridging generations of systems from the eutectic Sn-Pb era to the now-dominant SAC305 alloy. These interconnects have delivered sufficient mechanical, thermal, and electrical performance while enabling system integration and manufacturability across multiple technology nodes. But with the rise of artificial intelligence (AI) systems and high-performance computing (HPC) platforms the limits of what solder joints must endure are facing challenges. Increase in current carrying capability for higher power density, enhanced thermal cycling performance for large size components, manufacturing challenges, and system-level stress mitigation are stretching SAC305 interconnects, which served 30 years in industry, now to the edge of their capabilities. This seminar will examine the solder joint microstructure base evolution and the stability mechanism, the reasons for its decades-long availability and also visiting the potential limitations that are now emerging under AI systems and high-performance computing (HPC). We will explore degradation mechanisms in conventional solder alloys, contrast them with low-melting and alternative solder material systems, and assess how evolving reliability requirements reshape interconnect strategies. The discussion will consider whether conventional solder material can continue to serve as the backbone of packaging, or whether new roles or entirely reimagined interconnect solutions will be required to sustain the next era of AI and high-performance electronics.

Biography:

Dr. Tae-Kyu Lee is a Senior Technical Leader in the System Packaging and Reliability center (SPARC) in the Cisco Common Hardware Group (CHG) in San Jose, California. He served more than 20 years in the industry and academia on micro-electronics material reliability, solder and interconnect stability, Failure analysis and degradation mechanism, advanced packaging, superconductor, metallurgy and metal additive manufacturing. He received his Ph.D. degree in Materials Science and Engineering at University of California, Berkeley in 2004. Before joining the Cisco Technology and Quality (TnQ) group in 2006, he was a post-doc in the Lawrence Berkeley National Laboratory (LBNL) and served as an Associate professor in the Department of Mechanical and Materials engineering at Portland State University from 2015 to 2021 before rejoining Cisco. He is an active member in TMS, SMTA, IEEE-ECTC and serves as an associate editor in Journal of Electronic Materials. He has more than 3000 citations on authored and co-authored peer reviewed publications including book and book chapters on solder interconnect, reliability and microstructure evolution. He is also a recipient of a TMS Functional material division Distinguished Service award.

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