Dr. Vanessa Chen

Biography:

Vanessa Chen received her Ph.D. in Electrical and Computer Engineering from Carnegie Mellon University in 2013, where she worked on energy-efficient, ultra-high-speed ADCs with real-time calibration and interned at IBM T. J. Watson Research Center. She previously held circuit design roles at Qualcomm in San Diego and Realtek in Taiwan, focusing on self-healing RF and mixed-signal circuits. Her research explores AI-enhanced circuits and systems, including intelligent sensory interfaces, RF/mixed-signal hardware security, and ubiquitous sensing and computing. Dr. Chen is a recipient of the NSF CAREER Award, the CMU College of Engineering Dean’s Early Career Fellowship, and the IBM PhD Fellowship. She has served on program committees for ISSCC, VLSI, CICC, A-SSCC, and DAC, as an Associate Editor for several IEEE journals, and is currently an IEEE SSCS Distinguished Lecturer for 2025–2026.

Dr. Tim Hollis

DRAM standards have evolved tremendously over the last two-and-a-half decades, leading to diversification not only in the architecture of the memory array but also in that of the off-chip interface. Application-specific signaling channels have influenced the transceiver design nearly as much as system power and bandwidth requirements have. The influence of the multidrop server channel, along with a broad range of target environments, has led the DDR branch of JEDEC DRAMs to incorporate multi tap Decision Feedback Equalization to maximize flexibility, while shrinking supply voltages to facilitate energy reduction have led Low-Power DDR (LPDDR) to completely rethink the output driver structure. In parallel, Graphics DDR (GDDR) has reached speeds requiring nearly equal care of the external channel and the chip itself. The adoption of multi-level signaling in GDDR6x and GDDR7 to relax on-chip frequency requirements has only heightened the need for more rigorous co-design of transceiver, package and system characteristics. And, of course, the integration of silicon interposers to support High Bandwidth Memory (HBM) has driven a paradigm shift in memory interface design. With all of these adaptations, and many others not captured here, the splintering DRAM family continues to push the boundaries of single-ended signaling into the future. This presentation briefly explores what has driven the diversification in DRAM signaling schemes over the decades, will discuss the motivation behind present embodiments, and will project into the future to where the DRAM interface is likely headed (e.g., features and functions necessary for continued energy-efficient bandwidth scaling).

Biography:

Tim Hollis received the Ph.D. degree in electrical engineering from Brigham Young University, Provo, UT, USA, in 2007.  In 2006, he joined the Advanced Architecture Group at Micron Technology in Boise, Idaho, USA where he contributed to several pathfinding activities including the first-generation Hybrid Memory Cube. From 2012 to 2014, he worked as a chipset architect at Qualcomm in San Diego, CA, USA. He returned to Micron in 2014, where he currently leads the Interface Pathfinding Group as a Micron Fellow. He has published 18 articles in journals, conference proceedings, and technical magazines, and holds 274 issued U.S. and international patents. Dr. Hollis served as a member of the IEEE Workshop on Microelectronics and Electron Devices Organizing Committee from 2010-2024, including the General Chair in 2013. He has served on other IEEE conference committees as well as DesignCon’s Technical Program Committee from 2013 to 2015. From 2017 to 2020 he served as the Technology Editor for the IEEE Solid-State Circuits Magazine and as a Guest Editor for memory- and interface-related special issues in 2016 and 2019, respectively.