Advanced topics of Phase-Locked Loops (Bogdan Staszewski, Teerachot Siriburanon)
Hybrid Event: Monday, 8th December 2025 14:45 - 16:45, AGH University, building B-1 121 lecture hall.
Direct Frequency Modulation of ADPLLs
Bogdan Staszewski (UCD Dublin)
The past two decades has seen proliferation of all-digital phase-locked loops (ADPLL) for RF and high-performance frequency synthesis due to their clear benefits of flexibility, reconfigurability, transfer function precision, settling speed, frequency modulation capability, and amenability to integration with digital baseband and application processors. When implemented in nanoscale CMOS, the ADPLL also exhibits advantages of better performance, lower power consumption, lower area and cost over the traditional analog-intensive charge-pump PLL. In a typical ADPLL, a traditional VCO got directly replaced by a digitally controlled oscillator (DCO) for generating an output variable clock, a traditional phase/frequency detector and a charge pump got replaced by a time-to-digital converter (TDC) for detecting phase departures of the variable clock versus the frequency reference (FREF) clock, and an analog loop RC filter got replaced with a digital loop filter. The conversion gains of the DCO and TDC circuits are readily estimated and compensated using “free” but powerful digital logic.
The first talk covered the fundamentals of ADPLL. The second talk covered the loop response of ADPLL. This, third talk will cover the gear-shifting and direct frequency modulation capabilities of ADPLL.
Digitally Assisted Gain-Boosted Charge Sharing Locking for Next-Generation mm-Wave PLLs
Teerachot Siriburanon (UCD Dublin)
Abstract: Conventional charge-sharing locking (CSL) PLLs achieve low jitter but rely on large charge-sharing capacitors that periodically load the LC-tank, leading to high reference spurs. Our prior ping-pong (PP) CSL architecture alleviated this by using complementary charge-sharing paths and calibration loops to strengthen injection and improve spur behavior. Yet at mm-wave frequencies, CSL remains constrained by the tradeoff between injection strength and LC-tank loading, which limits tuning range and restricts operation at higher frequencies. This talk introduces a digitally-assisted gain-boosting (GB) CSL PLL that overcomes this constraint by sensing the CSL charge residue, digitally amplifying it, and reinjecting it through a small, minimally loading capacitor. This digitally assisted method preserves strong phase correction and high spectral purity with low spurious tones. Together, these advances demonstrate CSL as a high performance solution for next-generation mm-wave frequency synthesis.
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- AGH University
- Krakow, Malopolskie
- Poland 30-059
- Building: B1
- Room Number: 121