Data Center CPU, GPU and AI accelerators have evolved from monolithic System-on-Chip designs to heterogenous System-of-Chiplets to enable “More-than-Moore” scaling of system-level performance and energy efficiency at lower costs. This presentation highlights importance of interdisciplinary System-Technology Co-Optimizations (STCO) for architecting such heterogenous System-of-Chiplets. We will discuss architecture and design considerations for optimizing compute, memory and interconnect components, as well as trade-offs and co-optimization opportunities with process/packaging technologies, power delivery, thermals and system architectures. We will also highlight future trends and innovations required to drive continued performance and efficiency improvements for the AI era.

Biography:

Surhud Khare is a Principal Engineer in Data Center and AI Silicon Engineering Group at Intel Corporation. His areas of expertise include 3DIC process/packaging technologies, Silicon architecture/design optimizations for Heterogenous Integration and System-Technology Co-Optimization (STCO). Most recently, Surhud has contributed to Intel’s EMIB, Foveros and Foveros-Direct (Hybrid Bonding) technology definitions and physical architecture/design co-optimizations for multiple generations of Intel Xeon® and AI products. Surhud joined Intel in 2009 as part of Advanced Microprocessor Research Lab working on low-voltage circuits and CPU/SoC test-chip designs. Subsequently, he was a technical lead in Extreme-Scale Computing group working on energy-efficient interconnects/accelerator architectures and silicon/package prototype designs for Exascale Computing R&D projects.  Surhud holds M.S. degree in Electrical and Computer Engineering from Georgia Institute of Technology, Atlanta. He has co-authored 24 patents/publications and serves on technical program committees for several premier technical conferences. Surhud is a Senior Member of IEEE.