Joihn Lau of Unimicron Technology Corporation

Cu-Cu hybrid bonding is one of the flip chip assembly technologies. The advantages of hybrid bonding are: (a) higher density, (b) finer pad pitch, and (c) better performance. In this lecture, some fundamentals and more than 10 high-volume manufacturing products using hybrid bonding will be presented. On the other hand, co-packaged optics (CPO) are heterogeneous integration packaging methods to integrate the chiplets such as the optical engine (OE) which consists of photonic ICs (PIC) and the electrical engine (EE) which consists of the electronic ICs (EIC) as well as the switch ASIC (application specific IC). The advantages of CPO are: (a) to reduce the length of the electrical interface between the OE/EE (or PIC/EIC) and the ASIC, (b) to reduce the energy required to drive the signal, and (c) to cut the latency which leads to better electrical performance. In the next few years, we will see more implementations of Cu-Cu hybrid bonding and a higher level of heterogeneous integration of PIC and EIC, whether it is for performance, form factor, power consumption or cost.

Outline of the Talk:

Introduction

Cu-Cu Hybrid Bonding Fundamentals

HVM Cu-Cu Hybrid Bonding Products

·        Sony’s CIS with WoW

·        Sony’s CIS with WoWoW

·        Samsung’s CIS

·        AMD’s 3D V-Cache

·        Graphcore’s IPU

·        Apple’s M5 (GPU and CPU)

·        AMD’s MI300A (3.5D)

·        Samsung’s 3.5D

·        Broadcom’s 3.5D

·        Samsung’s HBM

·        SK Hynix’s HBM

·        Micron’s HBM

·        YMTC’s 3D NAND Flash

·        Western Digital’s 3D NAND Flash

Silicon Photonics

Data Centers

Optical Transceivers

Optical Engine (OE) and Electrical Engine (EE)

OBO (on-board optics)

NPO (near-board optics)

CPO (co-packaged optics)

3D Heterogeneous Integration of PIC and EIC

3D Heterogeneous Integration of ASIC Switch, PIC and EIC with Bridges

3D Heterogeneous Integration of ASIC Switch, EIC and PIC embedded in Glass-core Substrate

Summary and Recommendations

Biography:

John H Lau, with more than 40 years of R&D and manufacturing experience in semiconductor packaging, has published more than 530 peer-reviewed papers (385 are the principal investigator), 52 issued and pending US patents (31 are the principal inventor), and 24 textbooks. John is an elected IEEE fellow, IMAPS Fellow, and ASME Fellow and has been actively participating in industry/academy/society meetings/conferences to contribute, learn, and share.