John Lau of Unimicron Technology Corporation

As the semiconductor industry pushes beyond the limits of Moore’s Law, Copper-to-Copper (Cu-Cu) hybrid bonding has emerged as a cornerstone of advanced flip-chip assembly. This lecture provides a deep dive into the fundamentals of hybrid bonding, highlighting its pivotal advantages in achieving higher interconnect density, finer pad pitches, and superior electrical performance. To demonstrate its maturity, we will examine over ten high-volume manufacturing (HVM) products currently leveraging this technology.

The discussion then shifts to the frontier of Co-Packaged Optics (CPO)—a transformative heterogeneous integration method. By integrating Photonic ICs (PIC) and Electronic ICs (EIC) directly with switch ASICs, CPO addresses critical bottlenecks in modern data centers. Key benefits include:

• Reduced Interconnect Length: Minimizing the electrical interface between optical/electrical engines and the ASIC.

• Energy Efficiency: Drastically lowering the power required to drive high-speed signals.

• Latency Mitigation: Optimizing signal integrity for next-generation electrical performance.

We conclude by exploring the roadmap for the next few years, where the relentless demand for smaller form factors, lower power consumption, and cost-effective scaling will drive the convergence of Cu-Cu hybrid bonding and tighter PIC/EIC integration.

Outline of the Talk:

Introduction

Cu-Cu Hybrid Bonding Fundamentals

HVM Cu-Cu Hybrid Bonding Products

·        Sony’s CIS with WoW

·        Sony’s CIS with WoWoW

·        Samsung’s CIS

·        AMD’s 3D V-Cache

·        Graphcore’s IPU

·        Apple’s M5 (GPU and CPU)

·        AMD’s MI300A (3.5D)

·        Samsung’s 3.5D

·        Broadcom’s 3.5D

·        Samsung’s HBM

·        SK Hynix’s HBM

·        Micron’s HBM

·        YMTC’s 3D NAND Flash

·        Western Digital’s 3D NAND Flash

Silicon Photonics

Data Centers

Optical Transceivers

Optical Engine (OE) and Electrical Engine (EE)

OBO (on-board optics)

NPO (near-board optics)

CPO (co-packaged optics)

3D Heterogeneous Integration of PIC and EIC

3D Heterogeneous Integration of ASIC Switch, PIC and EIC with Bridges

3D Heterogeneous Integration of ASIC Switch, EIC and PIC embedded in Glass-core Substrate

Summary and Recommendations

Biography:

John H Lau, with more than 40 years of R&D and manufacturing experience in semiconductor packaging, has published more than 530 peer-reviewed papers (385 are the principal investigator), 52 issued and pending US patents (31 as the principal inventor), and 24 textbooks. John is an elected IEEE fellow, IMAPS Fellow, and ASME Fellow and has been actively participating in industry/academy/society meetings/conferences to contribute, learn, and share.