Using Architectural Simulation to Investigate Chiplets for Scalable and Cost Effective HPC Beyond Exascale

#Chiplets #heterogeneous #integration #modular #architecture #HPC

Chiplets have become a compelling approach to scaling and heterogeneous integration e.g. integrating workload-specific processors and massive bandwidth memory systems into computing systems; integrating die from multiple function-optimized process nodes into one product; integrating silicon from multiple businesses into one product. Chiplet-based products have been produced in high volume by multiple companies using proprietary chiplet ecosystems. Recently, the community has proposed several new standards (e.g., UCIe) to facilitate integration and interoperability of any compliant chiplet. Hyperscalers (e.g., Google, Amazon) are actively designing high volume products with chiplets through these open interfaces. Other communities are exploring the end-to-end workflow and tooling to assemble chiplet-based products. High performance computing can benefit from this trend. However, the performance, power, and thermal requirements unique to HPC, present many challenges to realizing a vision for affordable, modular HPC using this new approach. Architectural modeling and simulation will play a critical role in pathfinding for this new potential direction for HPC beyond Exascale.

-- Chiplets, heterogeneous integration, multi-physics challenges, modular architecture ...