A 1-1 MASH Noise Shaping SAR ADC with CLS Based Closed-Loop Residue Amplifier and On-Chip DWA CDAC Mismatch Correction
This talk presents a calibration-free recursive 1-1 MASH noise-shaping SAR
ADC implemented in 65-nm CMOS. By temporally reusing a single CDAC, residue
amplifier (RA), and comparator across both stages, the proposed architecture
inherently eliminates inter-stage gain and offset sensitivity without calibration or
additional conversion cycles. A duty cycle correlated level-shifting (CLS) enhanced
floating inverter amplifier achieves 68-dB effective gain with low power overhead. A 4-
bit MSB data-weighted averaging (DWA) scheme based on ADC/DAC dissociation
suppresses CDAC mismatch while remaining inactive during bit trials to minimize
switching energy. The design occupies an active area of 0.081mm2, consumes 12.07 μW,
and achieves a FoMs,DR of 172.48 dB.
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- Starts 16 March 2026 06:30 PM UTC
- Ends 23 March 2026 08:30 AM UTC
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Speakers
Shaleen of Tyndall National Institute, UCC Cork, Ireland.
A 1-1 MASH Noise Shaping SAR ADC with CLS Based Closed-Loop Residue Amplifier and On-Chip DWA CDAC Mismatch Correction
Biography:
Shaleen received a B.E in Electronics and Communication Engineering from R.G.P.V.
University, India and a received a M.Tech in Microelectronics and VLSI Design from
National Institute of Technology Patna, India(2020). He has worked for 1.5 years in
Silizium Circuit as an Analog design engineer.
Currently he is a PhD student in Tyndall National Institute, UCC Cork, Ireland. His
research interest lies in designing low power SAR ADCs, Analog Mixed signal designs,
PPG/SpO2 system.
Email:
Address:Tyndall National Institute, UCC Cork, Ireland, , Ireland
Shaleen of Tyndall National Institute, UCC Cork, Ireland.
A 1-1 MASH Noise Shaping SAR ADC with CLS Based Closed-Loop Residue Amplifier and On-Chip DWA CDAC Mismatch Correction
Speaker: Shaleen
Bio:
Shaleen received a B.E in Electronics and Communication Engineering from R.G.P.V.
University, India and a received a M.Tech in Microelectronics and VLSI Design from
National Institute of Technology Patna, India(2020). He has worked for 1.5 years in
Silizium Circuit as an Analog design engineer.
Currently he is a PhD student in Tyndall National Institute, UCC Cork, Ireland. His
research interest lies in designing low power SAR ADCs, Analog Mixed signal designs,
PPG/SpO2 system.
Biography:
Shaleen received a B.E in Electronics and Communication Engineering from R.G.P.V.
University, India and a received a M.Tech in Microelectronics and VLSI Design from
National Institute of Technology Patna, India(2020). He has worked for 1.5 years in
Silizium Circuit as an Analog design engineer.
Currently he is a PhD student in Tyndall National Institute, UCC Cork, Ireland. His
research interest lies in designing low power SAR ADCs, Analog Mixed signal designs,
PPG/SpO2 system.
Address:Tyndall National Institute, UCC Cork, Ireland, , Ireland
Media
| IEEE_EDS_NITP_Shaleen | 685.75 KiB | |
| Keynote_speaker_shaleen_1 | 1.06 MiB | |
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