Systematic Design of Bandgap Reference Circuit with Emphasis on Self-bias Loop Dynamics
With the scaling of supply voltages, sub-1V bandgap references are increasingly essential. This tutorial reviews modern architectures and digital designs, specifically addressing op-amp challenges like limited headroom and temperature-variant biasing. It provides a deep dive into self-bias loop dynamics and offers rigorous guidelines for mitigating systematic offset. Additionally, the session covers chopping techniques for random offset and concludes with robust startup circuit design tailored to the unique constraints of self-bias loops.
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- Bush House (SE) 2.02, Strand Campus
- Strand Campus
- London, England
- United Kingdom WC2R 2LS
- Building: King’s College London
- Room Number: SE 2.02
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- Co-sponsored by N/A
- Starts 20 March 2026 12:00 AM UTC
- Ends 30 March 2026 11:00 PM UTC
- No Admission Charge
Speakers
Dr. Rajasekhar
Systematic Design of Bandgap Reference Circuit with Emphasis on Self-bias Loop Dynamics
Biography:
Rajasekhar Nagulapalli received the B.Tech. degree in electrical engineering from Acharya Nagarjuna University, Guntur, India, in 2005, and the M.Tech. degree in microelectronics from the Indian Institute of Science, Bengaluru, India, in 2008 and PhD from Oxford Brookes, UK. From 2008 to 2011, he worked as PLL designer in Rambus, India After that he moved to IHP Germany to work on integrated optical chips. In 2013 he joined Inphi-Uk as a principal engineer and led a 100Gb/s PAM-4 transceiver project and successfully deployed more 100 million ports in data centres across the world. Since 2021, he has been working in Analog devices (ADI) and leading the automotive SERDES development. He has 16 approved US patents and 10 are still pending. He is the author of > 50 IEEE papers with >1000 citations.
Address:United Kingdom