Clock To Chip: Workshop on Static Timing Analysis and PnR

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IEEE PES University Student Branch in collaboration with IEEE CEDA Bangalore Chapter, is organizing a one-day technical workshop titled “Clock To Chip: Workshop on Static Timing Analysis and Place & Route (PnR)”.

This workshop is designed to introduce participants to the core concepts and industry practices involved in Static Timing Analysis (STA) and Physical Design (PnR), which are critical stages in modern VLSI chip design. Attendees will gain practical insights into timing closure, design optimization, and real-world chip implementation flows.

The session will be delivered by industry professionals, offering participants an opportunity to learn directly from experts and understand current trends in semiconductor design.

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