Invited talk on "Hardware Emulation based Security Verification"

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Hardware Emulation–Based Security Verification is a methodology that uses specialized hardware platforms (emulators) to validate and analyze the security properties of complex digital systems—especially modern System-on-Chips (SoCs)—by running designs at near-real speeds in a controlled environment.

Instead of relying only on software simulation (which is slow for large designs), hardware emulation maps the design (RTL) onto dedicated emulation hardware. This allows engineers to execute realistic workloads, firmware, and operating systems while observing how the system behaves under normal and adversarial conditions.


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  • Starts 29 March 2026 05:00 AM UTC
  • Ends 03 April 2026 05:00 AM UTC
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Sujan

Topic:

Hardware Emulation based Security Verification

Hardware Emulation–Based Security Verification is a methodology that uses specialized hardware platforms (emulators) to validate and analyze the security properties of complex digital systems—especially modern System-on-Chips (SoCs)—by running designs at near-real speeds in a controlled environment.

Instead of relying only on software simulation (which is slow for large designs), hardware emulation maps the design (RTL) onto dedicated emulation hardware. This allows engineers to execute realistic workloads, firmware, and operating systems while observing how the system behaves under normal and adversarial conditions.

Biography:

Dr. Sujan Saha is a Postdoctoral Associate in the Department of Electrical and Computer Engineering at the University of Florida. He received his Ph.D. in Electrical and Computer Engineering from the University of Florida in 2023. He also holds an M.Sc. in Computer Engineering from the University of California, Riverside, and a B.Sc. in Electrical and Electronic Engineering from the Bangladesh University of Engineering and Technology (BUET). Dr. Saha’s research focuses broadly on System-on-Chip (SoC) security, with emphasis on FPGA-based embedded SoC security, the application of AI/LLMs to hardware security, hardware-assisted security verification, and runtime security monitoring. His scholarly contributions include a book chapter, a pending patent, and 40 peer-reviewed publications in leading venues such as DATE, ASP-DAC, HOST, ICCD, GLSVLSI, ISVLSI, AsianHOST, IEEE Design & Test, IEEE Access, ACM TRETS, and RTCSA. He has served on the technical program committees of IEEE HOST, GLSVLSI, and RTAS, and is a regular reviewer for journals including IEEE Access, TIFS, ACM Computing Surveys, Proceedings of the IEEE, and TCAD.