SSCS DL Presentation - Fractional-N Phase-Locked Loops Using Harmonic-Mixer-Based Feedback and Noise Cancellation
Title: Fractional-N Phase-Locked Loops Using Harmonic-Mixer-Based Feedback and Noise Cancellation
Abstract: Frequency synthesizers are an integral part of various applications, such as wireless and wireline communication systems. The generation of frequency sources with low phase noise under limited power, area, and many other factors has been an ongoing challenge over the years. Especially for the fractional-N phase-locked loops (PLLs), the suppression of quantization noise (Q-noise) and spurs has been one of the main challenges. Architectures based on quantization error cancellation, either in the time domain using digital-to-time converters or in the voltage domain using digital-to-analog converters, have been popular in recent years. However, the circuits used for the cancellation are often affected by PVT-related gain errors and non-linearity, requiring intensive digital calibration to prevent severe performance degradation. In this talk, we introduce some harmonic-mixer-based fractional-N PLL architectures that avoid the amplification of the Q-noise by the loop. With this concept, we can effectively suppress the contribution of the Q-noise at the PLL output without applying intensive calibration.
Tetsuya Iizuka received the B.S., M.S., and Ph.D. degrees in electronic engineering from the University of Tokyo, Tokyo, Japan, in 2002, 2004, and 2007, respectively. From 2007 to 2009, he was with THine Electronics Inc., Tokyo, as a High-Speed Serial Interface Circuit Engineer. He joined the University of Tokyo in 2009, where he is currently a Professor with the Department of Electrical Engineering and Information Systems, School of Engineering. From 2013 to 2015, he was a Visiting Scholar with the University of California at Los Angeles, Los Angeles, CA, USA. His current research interests include data conversion techniques, high-speed analog integrated circuits, digitally assisted analog circuits, and VLSI computer-aided design.
He was a TPC member of ISSCC from 2013 to 2017 and CICC from 2014 to 2019. He is also serving as a member of the IEEE Asian Solid-State Circuits Conference (A-SSCC) and the IEEE VLSI Symposium on Circuits Technical Program Committees. Since 2025, he has been serving as a distinguished lecturer of the IEEE SSCS.
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Tetsuya
: Fractional-N Phase-Locked Loops Using Harmonic-Mixer-Based Feedback and Noise Cancellation
Abstract: Frequency synthesizers are an integral part of various applications, such as wireless and wireline communication systems. The generation of frequency sources with low phase noise under limited power, area, and many other factors has been an ongoing challenge over the years. Especially for the fractional-N phase-locked loops (PLLs), the suppression of quantization noise (Q-noise) and spurs has been one of the main challenges. Architectures based on quantization error cancellation, either in the time domain using digital-to-time converters or in the voltage domain using digital-to-analog converters, have been popular in recent years. However, the circuits used for the cancellation are often affected by PVT-related gain errors and non-linearity, requiring intensive digital calibration to prevent severe performance degradation. In this talk, we introduce some harmonic-mixer-based fractional-N PLL architectures that avoid the amplification of the Q-noise by the loop. With this concept, we can effectively suppress the contribution of the Q-noise at the PLL output without applying intensive calibration.
Biography:
Tetsuya Iizuka received the B.S., M.S., and Ph.D. degrees in electronic engineering from the University of Tokyo, Tokyo, Japan, in 2002, 2004, and 2007, respectively. From 2007 to 2009, he was with THine Electronics Inc., Tokyo, as a High-Speed Serial Interface Circuit Engineer. He joined the University of Tokyo in 2009, where he is currently a Professor with the Department of Electrical Engineering and Information Systems, School of Engineering. From 2013 to 2015, he was a Visiting Scholar with the University of California at Los Angeles, Los Angeles, CA, USA. His current research interests include data conversion techniques, high-speed analog integrated circuits, digitally assisted analog circuits, and VLSI computer-aided design.
He was a TPC member of ISSCC from 2013 to 2017 and CICC from 2014 to 2019. He is also serving as a member of the IEEE Asian Solid-State Circuits Conference (A-SSCC) and the IEEE VLSI Symposium on Circuits Technical Program Committees. Since 2025, he has been serving as a distinguished lecturer of the IEEE SSCS.