RISC-V Workshop Session 3: Multi-cycle Core
#ieee
#computer-society
#risc-v
#pipelining
#processors
This session covers the design of multi-cycle and pipelined architectures in RISC-V systems. It introduces the key registers used in a multi-cycle core, explains how instructions are executed across stages. The session also examines pipeline hazards, their impact on performance and techniques for improving overall processor efficiency.
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- Nairobi, Nairobi
- Kenya
- Building: Strathmore University
- Room Number: MSB 5
Speakers
Jacob Kirera
Cynthia Maina
Felix Onsongo