David Keezer of Eastern Institute of Technology

Technical seminar with the following abstract: 

Today’s integrated circuits may contain billions of transistors and operate at multiple gigahertz clock rates.  The communication port input and output aggregate bandwidths can easily exceed a terahertz (e.g. 800G and 1.6T PCIe and fiber-optic ports).  Furthermore, some ICs support multiple high-speed communication ports as well as high-performance analog/RF signals. All these critical features need precise testing to ensure product quality.  While existing automated test equipment (ATE) can handle the bulk of “mainstream” IC test requirements, they are not well-suited for these most advanced applications and are not easily adapted to new test challenges of future devices that may use entirely new signaling protocols.   There is therefore a “gap” between the ability of ATE and the test needs of the most advanced devices.  To address this problem, we are assembling an FPGA-based test-development platform that can quickly adapt to future test requirements.  This presentation will describe the strategy and system architecture and show some early demonstrations for testing mixed analog/digital ICs as well as communication channels operating up to 224 Gbps per lane.

Biography:

Professor Keezer received the PhD. degree in electrical and electronic engineering from Carnegie-Mellon University in 1983. His master’s degree was from Caltech in 1979 and bachelor’s degree from UC Berkeley in 1978.  He has worked in industry for Intel, IBM, Xerox PARC, and Harris Corporation. From 1995 to 2022 he held positions as associate professor, professor, and professor emeritus at the Georgia Institute of Technology (Georgia Tech). In 2010, he was elected as an IEEE Fellow and recently became an IEEE Life Fellow. He has published more than 270 papers in international journals and conferences, supervised 16 PhD students and 19 master's students, participated in more than 100 PhD defense committees, and taught thousands of doctoral, masters, and undergraduate students. He has served as a reviewer and editor for numerous international academic conferences and journals. He has chaired sessions at the IEEE International Test Conference, IEEE VLSI Test Symposium, IEEE Electronic Packaging Technology Conference and other international conferences. He currently serves as a chair professor in the College of Information Science and Technology at Eastern Institute of Technology, Ningbo. His research focuses on high-performance electronic system design and testing methods, high-speed logic system design, and advanced electronic packaging research.

Address:Ningbo, China