Hardware Design Thinking Workshop
#Hardware
#Design
#Digital
#VLSI
#FPGA
#RTL
#System
#Architecture
#Thinking
#Waveform
#Analysis
#FSM
#Sequential
#Logic
#Electronics
#ASIC
#Verification
#Timing
#Embedded
#Systems
#Semiconductor
#IEEE
#CEDA
#Hands-on
#Workshop
#Silicon
IEEE CEDA Bangalore Chapter, in association with Sai Vidya Institute of Technology, are organizing a Hardware Design Thinking Workshop aimed at students and early-career professionals interested in digital hardware design and architecture.
This hands-on, problem-driven workshop focuses on real-world hardware design challenges through waveform analysis, block-diagram thinking, and practical digital design exercises. Participants will explore concepts such as FSMs, counters, flip-flops, logic gates, synchronous pipelines, and flow control methodologies while learning how hidden design assumptions can lead to silicon bugs.
The workshop will be conducted by industry experts:
- Milind Parelkar — Principal Engineer, Qualcomm
- Palash Khandale — Staff Engineer, ARM
Workshop Highlights
- Hands-on learning with real-world hardware design scenarios
- Interactive waveform drawing and timing analysis sessions
- Practical design exercises using FSMs and sequential logic
- Architecture-focused problem solving and design thinking
- Collaborative discussions, whiteboard sessions, and Q&A
Date and Time
Location
Hosts
Registration
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- Sai Vidya Institute of Technology
- 5H95+CP2, via, Yelahanka, Rajanukunte
- Bengaluru, Karnataka
- India 560119
Speakers
Milind Parelkar of Principal Engineer, Qualcomm
Palash Khandale of Staff Engineer, ARM