PCBA Mfg. Facility Tours followed by three Presentations about electronics manufacturing quality and packaging as a root cause of failure
The meeting will start with PCBA Mfg. Facility Tours followed by three Presentations which are as follows:
- Driving Quality in Electronics Manufacturing: Advanced Packaging, Process Tools, and Smart Package Selection. Presented by Matteo Forgione of Forgione Engineering
- Packaging Selection as a Root Cause of Failure in Microelectronics Chip Tray and Waffle Pack Systems. Presented by Katherine Kutina of Forgione Engineering
- What changed at APEX and Why it Matters, a review of APEX 2026. Presented by Leo Lambert of Eptac Corporation
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Any questions, please contact Michael Jansen @ Mack Technologies at mjansen@macktech.com
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- Co-sponsored by SMTA Boston Chapter, iMAPS NE Chapter, and the IEEE Boston Reliability Chapter
Speakers
Matteo of Forgione Engineering
Driving Quality in Electronics Manufacturing: Advanced Packaging, Process Tools, and Smart Package Selection
Electronics manufacturers face increasing pressure to improve yield, reduce scrap, and maintain consistent quality as device complexity and performance demands continue to rise. This presentation highlights how Forgione Engineering addresses these challenges through a comprehensive approach that combines advanced packaging solutions for bare die and complex assemblies, industry-standard tools for inspection, rework, and production, and the development of intelligent software for package selection. Attendees will gain insight into practical, proven methods to enhance process control, minimize defects, and accelerate decision-making in package selection. By bridging the gap between design, packaging, and manufacturing, this session will demonstrate how integrated engineering solutions can drive measurable improvements in reliability, efficiency, and overall product quality.
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Biography:
Matteo Forgione is the founder of Forgione Engineering, Inc. (2008) and has worked with microelectronics manufacturers since 2017 to develop tools, devices, and processes implemented to increase quality and reduce scrap rates. Complicated, multi-disciplinary design and manufacturing projects have been his specialty since the beginning. For the microelectronics industry, Forgione provides standardized FOD (foreign object debris) detection, ESD Packaging, custom waffle packs, critical component protective packaging, rework, surface prep, fixtures, tools, and solvent cleaning products. Mr. Forgione has also worked as a Visiting Faculty Teaching Professor at the University of Massachusetts Lowell in the Mechanical Engineering Department since 2020. He has been a registered licensed professional engineer in the Commonwealth of Massachusetts since 2015.
Address:Forgione Engineering, , United States
Katia of Forgione Engineering
Packaging Selection as a Root Cause of Failure in Microelectronics Chip Tray and Waffle Pack Systems
Component Out of Pocket (COOP) events, Jammed Component In Pocket (JCIP) events, components being crushed in packaging or broken during transit due to improperly sized pockets in chip trays and waffle pack assemblies, leading to foreign object debris (FOD) generation are costly failures in microelectronics manufacturing. Millions of dollars per year in scrap, rework, equipment damage, wasted resources and time, as well as program delays occur. These in-process failures may seem like coincidence or random occurrence but can be traced back to improper packaging selection. Lack of knowledge of the complete downstream process, transportation risks, product protection, and required presentation to automation equipment are major detriments to manufacturers’ yields. A review of the industry standard packaging options, applications, and their contribution to the risk of damage depending on component sizes and types is presented. Process engineers and factory managers tasked with resolving these problems as they arise can obviate downstream disruptions and waste by early-stage planning within each organization, promulgating specific supplier packaging requirements for this purpose. The development of an industry-wide incoming supplier packaging standard for bare die ICs and microelectronics components that specify the use of chip tray and waffle pack systems in a way that prevents unnecessary losses is proposed; eliminating the longstanding “if it fits, it ships” supplier requirements.
Biography:
Katherine Kutina is an R&D and Aerospace Engineer at Forgione Engineering in Lowell, MA. She earned a B.S. in Aeronautical and Astronautical Engineering from MIT, with 3 years of previous industry experience at multiple startups in the medical device industry as an R&D, material science, and mechanical engineer. Now leading technological development in the aerospace, microelectronics, and materials science fields, and partners with the company president to define and execute the company’s long term-term vision and strategic trajectory. She enjoys working directly with clients to transform designs into industry standard products. Outside of work, she enjoys painting, hiking, and dancing.
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Address:Forgione Engineering, , United States
Leo of Eptac Corporation
What changed at APEX and Why it Matters: a review of APEX 2026
Presentation will discuss recent updates in IPC specifications, the Name Change from IPC to Global Electronic Association, the work & development of specifications and training programs from subject matter experts, and new materials added to the specifications and training programs. Leo will also discuss the miniaturization of the products and their impact on the specifications and training programs, from 3D boards to High Density (HDI) and to Ultra High Density boards (UHDI)
Biography:
As Technical Director for EPTAC Corporation, Leo oversees content of course offerings and provides customers with expert consultation. He has over forty years of experience with expertise in soldering, metallurgy and cleaning processes. He’s co-author of the industry’s most popular publications, including the IPC-A-600 Training Program, “The Acceptability of Printed Boards”. Leo was inducted into the IPC Raymond E. Pritchard Hall of Fame, is the Author of “Soldering for Electronic Assemblies” and numerous papers on Soldering and Cleaning, Chairman of the Assembly & Joining Committee, Recipient of IPC President Award, Charter member of J-STD-001 Committee and Active participant of the following IPC committees: ANSI-J-STD-001, IPC-A-610, IPC-A-600, IPC-6012, J-STD-002, J-STD-003, IPC/WHMA-A-620, J-STD-001 & IPC-A-610 Handbook.
Address:Eptac Corporation, , United States
Agenda
Agenda:
5:00 PM – 6:30 PM Registration, Networking, Table Top Displays/Demos, Manufacturing Facility Tours
6:00 PM – 7:00 PM Italian Buffet Dinner
7:00 PM – 7:30 PM Announcements, Presentation: Overview of Mack Technologies
7:30 PM – 8:00 PM Presentation 1 – Driving Quality in Electronics Mfg.: Advanced Packaging, Process Tools & Smart Package Selection, Q&A
8:00 PM – 8:30 PM Presentation 2 – Packaging Selection as a Root Cause of Failure in Microelectronics Chip Tray, & Waffle Pack Systems, Q&A
8:30 PM – 9:15 PM Presentation 3 – What changed at APEX and Why it Matters, a review of APEX 2026, Q&A
9:15 PM – 9:30 PM Closing Announcements, Meeting Adjourns