Improving Integrated Circuit Advanced Packaging Manufacturability with Thermomechanical Simulation

#Fabrication #Semiconductor #Tour

High-tech applications like autonomous driving, 5G communication, and especially artificial intelligence and machine learning are driving the semiconductor industry to increase microchip complexity and processing power more than ever. At the same time, Moore’s Law, which postulates that the number of transistors in an integrated circuit doubles every two years and has roughly held since 1975, is nearing its physical limit. As a result, the electronics industry has moved towards advanced packaging solutions in the past decade.

Broadly, advanced packaging refers to incorporating multiple chips within a single electronic component, often utilizing heterogeneous integration, meaning the different chips within the package have different functions. Additionally, advanced packaging typically includes some degree of vertical stacking among the multiple chips. Stacked structures reduce interconnect length by orders of magnitude, leading to higher bandwidths, capacities, and data rates.

While these stacked features are extremely powerful from an electrical perspective, they are also extremely complex from a structural and material perspective. A single advanced package will often include silicon chips, a silicon or glass interposer, and a glass fiber-reinforced organic substrate all attached to each other with various solder and copper interconnects. The total interconnect count can easily be in the hundreds of thousands, and the smallest interconnects can scale down several orders of magnitude from the overall package size. The whole package may then be covered with a protective polymer overmold or utilize a copper or steel stiffener or lid.

These packages require complex fabrication processes involving several high-temperature events like multiple solder reflows, copper interconnect annealing, and polymer cures. The variation in Young’s Modulus and coefficient of thermal expansion (CTE) throughout the structure can create stress concentrations that fracture interconnects across dissimilar materials during these many manufacturing-related temperature excursions. Furthermore, even if the advanced package can be fabricated completely without issue, soldering it to a circuit board presents a potential problem. The CTE mismatches within the package can warp the package enough to create soldering defects during board-level reflow.

The rapidly evolving nature of advanced packaging, the extreme number of interconnects within a single package, and the high production cost of cutting-edge semiconductors demand that simulation play a role in evaluating the manufacturability of novel advanced package designs. This presentation will overview key manufacturing processes that can be evaluated with thermomechanical FEA for an advanced package design. It will also investigate strategies for dealing with modeling complications specific to advanced packages, including how to address interconnect scaling issues with layer simplification and submodeling and when to consider temperature-dependent and nonlinear material properties.

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• Ansys Corporation
• 9000 Virginia Manor Road
• Beltsville, Maryland
• United States 20705
• Room Number: Suite 290

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• Starts 06 June 2026 01:00 AM UTC
• Ends 18 June 2026 02:00 AM UTC
• No Admission Charge

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  5:30 - 6:00 pm	Gather and introductions
  6:00 - 6:45 pm	Ansys lab tour and electronics capabilities overview
  6:45 - 7:30 pm	Ansys speaker presentation
  7:30 pm	Wrap-up

Registration required by 10 pm June 17. Tour is not limited to US nationals but Ansys requires citizenship information for attendees.