IEEE Lecture - Co-Design and Tools for Heterogeneous Integration - Challenges and Opportunities
The advent of artificial intelligence, high-performance computing, data centers, health, automotive and communication is driving the quest for more creative integration methods. Future packaging technologies will exhibit high interconnect densities and large numbers of diverse components and devices. Such schemes are expected to offer relaxed transactions between components, increased bandwidth, and better energy efficiency. To achieve these potentials, the implementation of these systems will require assistance from design tools that can handle unmatched levels of complexity and highly complex computational challenges. This talk will address recent developments in computer-aided design (CAD) tools for interconnects and packages. We will emphasize the signal integrity, power and bandwidth requirements. Multi-domain and multi-physics challenges will be explored as well as potential co-design solutions.
Date and Time
Location
Hosts
Registration
-
Add Event to Calendar
- 6455 Lusk Blvd
- San Diego, California
- United States 92121
- Building: Qualcomm Building Q Auditorium
- Starts 08 June 2026 07:00 AM UTC
- Ends 24 July 2026 07:00 AM UTC
- No Admission Charge
Speakers
José E. Schutt-Ainé
Biography:
José E. Schutt-Ainé is with the faculty in the Electrical and Computer Engineering Department at the University of Illinois at Urbana-Champaign. His research interests are on signal integrity for high-speed digital and high-frequency applications. He received the 2024 IEEE-EPS Outstanding Sustained Technical Contribution Award. Dr. Schutt-Ainé is an IEEE Fellow, EPS Distinguished Lecturer, and served as Co-Editor-in-Chief of the IEEE Transactions on Components, Packaging and Manufacturing Technology (T-CPMT) from 2007 to 2018. He is currently co-chairing the co-design chapter of the IEEE-EPS Co-Design Chapter of the Heterogeneous Integration Roadmap.