Dual Seed Semi-Additive and Damascene Processes: Enabling Fine-Pitch Interconnects for Advanced Packaging

#advanced #packaging #damascene #deposition #high #aspect #ratio #via
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-- Next-Gen copper deposition, scaling, AI solutions, advanced copper, high-aspect-ratio vias ...


     As AI, high-performance computing, and heterogeneous integration continue to scale, advanced packaging is facing growing interconnect challenges across redistribution layers, IC substrates, HDI boards, silicon vias, and emerging glass-core platforms. Higher bandwidth and larger package form factors require finer wiring, smaller vias, higher fan-out density, and more reliable vertical interconnects. In this context, copper seed formation and via metallization are becoming increasingly important bottlenecks for next-generation package and substrate scaling.
     Conventional copper deposition technologies, including physical vapor deposition, electroless plating, and electroplating, each play essential roles in today’s manufacturing flows. However, as via structures become smaller, deeper, rougher, or higher in aspect ratio, limitations such as step coverage, liquid circulation, process uniformity, and seed-layer continuity become more difficult to manage. These challenges are especially relevant across multiple interconnect layers, including motherboard HDI PCBs, IC substrates, RDL, memory and interposer silicon vias, and Si BEOL metal, etc.
     This presentation will introduce Nano Copper Deposition as a solution family for AI-era interconnect scaling. The talk will cover DeepVia™ HDI for high-aspect-ratio via metallization in motherboard HDI PCBs, DS-SAP™ for resolving the trade-off between thin surface seed layers and robust via coverage in IC substrates, and other applications such as Dual Seed Damascene for fine and high-aspect-ratio damascene structures in BEOL and RDL applications, and DeepVia™ Silicon for memory and interposer silicon vias. The discussion will highlight how these approaches can support higher I/O density, improved escape routing, reduced layer-count dependency, and broader process flexibility for next-generation advanced packaging.



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  • Starts 25 June 2026 07:00 AM UTC
  • Ends 07 August 2026 12:00 AM UTC
  • No Admission Charge


  Speakers

Shinya Shimizu of Elephantech Inc.

Biography:

Shinya Shimizu founded Elephantech Inc. — then known as AgIC Inc. — in 2014 and assumed the role of Representative Director and President. Elephantech was the first company in the world to commercialize a circuit formation process using proprietary copper nanomaterials. The company contributes to the realization of high-density, high-thermal-performance packaging required in the AI era.  Prior to founding the company, he worked at McKinsey & Company from 2012, where he engaged primarily in consulting for the manufacturing sector.  He holds a Master’s degree from the Department of Information and Communication Engineering, Graduate School of Information Science and Technology, The University of Tokyo.

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