PAETRIX Logic Design
The logic design competition was conducted on 27 April 2026 from 10:00 AM to 12:30 PM as a part of "PAETRIX " a four day National level tech summit. A total of 4 teams participated in the competition including team from other college also, making the competition more diverse and competitive.
There were 5 rounds, round 1 was technical quiz, round 2 was to find the output of the given circuit, round 3 was to solve the given Boolean expression, round 5 was to correct the error in the given circuit and final round was to build a circuit and show the output.
Judging was based on marks given in each rounds.
Winners:Team Ec royals - PA college of engineering mangalore
Runners:Team SDMIT- ujire
The prizes were awarded by Dr. Asiya hazareena and prof. Mohammed Hussain. The event successfully enhanced the students practical knowledge on logic gates and increased their confidence.
The event was coordinated by Faculty coordinator prof. Arshiya Nazneen N Z(ECE)along with student coordinators Mohammed Zohan (ECE) and Mohammed Sinan (ECE).
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- VLSI Lab, Department of ECE
- P. A. College of Engineering (PACE), Near Mangalore University, Kudla, Kalarangala
- Mangalore, Karnataka
- India 574153