Faculty Development Programme on VLSI Design Tape-Out Readiness: Concepts, Tools, AI Workflows & Automation
The IEEE CEDA Bangalore Chapter, in collaboration with the IEEE PES Bangalore Section and the Departments of ECE and EEE, PES University, is organizing a 5-day Faculty Development Programme (FDP) on "VLSI Design Tape-Out Readiness: Concepts, Tools, AI Workflows & Automation."
This programme is designed to equip faculty members, researchers, and academicians with the knowledge and practical skills required to understand modern VLSI design methodologies and prepare for industry-ready tape-out workflows.
The FDP covers the complete VLSI design flow, including digital, analog, and mixed-signal IC design, RTL design, synthesis, static timing analysis, physical design, verification, sign-off, DFT/DFX, reliability, and SoC integration. Participants will also gain exposure to emerging AI-driven VLSI workflows, automation techniques, and hands-on training using industry-standard EDA tools.
The sessions will be delivered by distinguished experts from academia and the semiconductor industry, providing participants with practical insights into current design practices and future trends.
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- PES University
- 100 Feet, Ring Rd, Dwaraka Nagar, Banashankari
- Bengaluru, Karnataka
- India 560085