ASIC Implementation Bootcamp – From Synthesis to GDS-II Tapeout using cadence Virtuoso and Innovus : vTools Events

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ASIC Implementation Bootcamp – From Synthesis to GDS-II Tapeout using cadence Virtuoso and Innovus

#IEEE #Design #CH11092 #CEDA #libraries #learning #integrity #ic-design #estimation #education #communication

The ASIC Implementation Bootcamp – From Synthesis to GDS-II Tapeout was organized during the weekends of April 2026 at the Skill Lab, K.S. School of Engineering and Management by the Department of Electronics and Communication Engineering and IEEE KSSEM Student Branch in association with the IEEE CEDA Student Chapter, KSSEM and the IEEE Education Society Student Chapter, KSSEM. The program was delivered by Mr. Lalit Sahoo, Senior Physical Design Engineer, and aimed to provide students with practical exposure to ASIC Physical Design methodologies and semiconductor backend implementation workflows.

The bootcamp was designed to bridge the gap between academic learning and industrial practices by offering hands-on training using industry-standard tools such as Cadence Virtuoso and Cadence Innovus. The sessions focused on the complete ASIC backend design flow, enabling students to understand real-world semiconductor design practices followed in the industry.

The program was conducted over four weekends, with each session covering a specific stage of the ASIC Physical Design flow.

Day 1 introduced the fundamentals of ASIC design flow, covering the complete semiconductor backend process from RTL specification to GDS-II TapeOut. Students were familiarized with Cadence tools, RTL-to-Gate synthesis, technology libraries, timing constraints, and optimization techniques. Demonstrations were provided on synthesis flow and backend design environments used in the semiconductor industry.

Day 2 focused on Physical Design inputs and Floor Planning. Students were introduced to key input files such as Verilog netlists, SDC, LEF, technology libraries, and TLU+ files. The session also covered floor planning concepts including die area estimation, core utilization, macro placement, IO planning, power planning, and congestion management. Hands-on exercises were conducted using Cadence tools to reinforce implementation concepts.

Day 3 covered Placement, Clock Tree Synthesis (CTS), and Static Timing Analysis (STA). Topics included global placement, legalization, optimization techniques, scan chain reordering, and timing closure concepts. Students were also introduced to setup and hold analysis, slack computation, clock skew, and timing optimization strategies used in ASIC backend flows.

Day 4 focused on Routing, Signoff verification, and GDS-II generation. The session included global and detailed routing, congestion handling, signal integrity considerations, filler insertion, and metal fill concepts. Signoff checks such as DRC, LVS, and timing verification were also discussed, leading to final GDS-II Tapeout understanding. The session concluded with an interactive discussion on industry expectations, career opportunities, and skill development in semiconductor physical design.

Overall, the bootcamp provided comprehensive hands-on exposure to ASIC implementation flow, enabling students to gain practical knowledge of backend VLSI design methodologies and strengthening their readiness for careers in semiconductor and VLSI industries. The resource person’s enthusiasm and selfless dedication to teaching were truly commendable. His advice to students – “ Take time to choose your domain, master its skills, and never look back”-resonated deeply with the audience.