Workshop on System Design using Simulink and HDL Coder/Verifier Workflows
Following the inauguration of the IEEE CEDA Student Chapter, a hands-on workshop was conducted on system design using MATLAB, Simulink, HDL Coder, and HDL Verifier workflows. The workshop was led by Dr. Anand Mukhopadhyay, Senior Engineer in the Education Team at MathWorks India Pvt. Ltd., who holds a Ph.D. in Neuromorphic Computing from IIT Kharagpur and is a Senior Member of IEEE.
The session introduced participants to model-based design methodology, automatic VHDL/Verilog code generation, and FPGA implementation, with live demonstrations of system modeling in Simulink and verification workflows using HDL Verifier. The workshop aimed to give students practical exposure to industry-standard Electronic Design Automation (EDA) tools used for FPGA and digital system development.
An interactive Q&A segment allowed participants to discuss applications of MATLAB and Simulink in research and industry, HDL code generation and verification techniques, FPGA implementation challenges, and career opportunities in VLSI, FPGA, and the semiconductor industry.
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Date and Time
Location
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- ECE Seminar Hall (Second Floor) Department of Electronics and Communication Engineering
- KLE Technological University
- Hubballi, Karnataka
- India 580031
Speakers
Dr. Anand Mukhopadhyay of MathWorks India Pvt. Ltd.
Lakshmanan Balasubramanian