Glass-Core Packaging and Its Reliability
#glass
#core
#interposer
#substrate
#2.5D
#3D
#AI
#packaging
#advanced
In the past few years, because of high-performance computing (HPC) driven by artificial intelligence (AI) and data centers in this AI era, packaging using glass-core substrates has been attracting lots of traction. For example, among others, Intel’s one-trillion-transistors application processor with glass-core substrate is to be shipped by the end of 2030 (announced September 2023) and TSMC’s chip-on-panel-on-substrate (CoPoS) with glass-core interposer is to be shipped in Q1 of 2029 (announced April 2025). In this lecture, a brief fundamental of through-glass via (TGV) and redistribution-layers (RDLs) of glass packaging will be presented. The advantages and disadvantages of glass, silicon, and organic will be discussed. Panel-level packaging vs. wafer-level packaging and the panel size will also be provided. Finally, the effects of coefficient of thermal expansion (CTE) of glass-core substrate on the solder joint reliability on printed circuit board (PCB) will be presented. Some recommendations will be provided.
Date and Time
Location
Hosts
Registration
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SEMI World Headquarters
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673 South Milpitas Blvd
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Milpitas, California
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United States
95050
- Starts
09 July 2026 07:00 AM UTC
- Ends
24 September 2026 07:00 PM UTC
- No Admission Charge
Speakers
John Lau of Unimicron
Biography:
John Lau, with more than 40 years of R&D and manufacturing experience in semiconductor packaging, has published more than 540 peer-reviewed papers (390 are the principal investigator), 54 issued and pending US patents (35 are the principal inventor), and 25 textbooks. John is an elected IEEE Fellow, IMAPS Fellow, and ASME Fellow and has been actively participating in industry/academy/society meetings/conferences to contribute, learn, and share. He is an IEEE Distinguished Lecturer.
Address:United States
