IEEE CASS Rio Chapter Lecture – Using Fault Tolerant RISC-V Processors and Fault Tolerant AI engines into FPGAs for Earth Observation and other High Reliable Applications

#circuits #microelectronics #systems #design #machine-learning #application #ai-accelerators #memory #CAS #processor #earth
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This talk presents recent advances in the design and deployment of fault-tolerant RISC-V processors and fault-tolerant AI engines implemented on SRAM-based FPGAs targeting Earth Observation and other mission-critical systems. The presentation discusses architectural and system-level techniques to mitigate soft errors, including modular and distributed redundancy, selective hardening, error detection and correction mechanisms, configuration memory scrubbing, and resilience-aware design methodologies. Particular emphasis is placed on open RISC-V soft-cores and AI accelerators for on-board inference, highlighting trade-offs between reliability, performance, power, and resource utilization.


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  • Centro de Tecnologia da UFRJ
  • Cidade Universitária, Centro de Tecnologia
  • Rio de Janeiro, Rio de Janeiro
  • Brazil 21941972
  • Room Number: bloco H, sala 322
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  • Starts 17 July 2026 03:00 AM UTC
  • Ends 06 August 2026 03:00 AM UTC
  • No Admission Charge

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Fernanda Kastensmidt

Topic:

Using Fault Tolerant RISC-V Processors and Fault Tolerant AI engines into FPGAs for Earth Observation and other High Rel

This talk presents recent advances in the design and deployment of fault-tolerant RISC-V processors and fault-tolerant AI engines implemented on SRAM-based FPGAs targeting Earth Observation and other mission-critical systems. The presentation discusses architectural and system-level techniques to mitigate soft errors, including modular and distributed redundancy, selective hardening, error detection and correction mechanisms, configuration memory scrubbing, and resilience-aware design methodologies. Particular emphasis is placed on open RISC-V soft-cores and AI accelerators for on-board inference, highlighting trade-offs between reliability, performance, power, and resource utilization.

Biography:

Fernanda holds a degree in Electrical Engineering from the Federal University of Rio Grande do Sul (1997), a master's degree in Computer Science from the Federal University of Rio Grande do Sul (1999) and a PhD in Computer Science from the Federal University of Rio Grande do Sul (2003). Fernanda is a Full Professor at the Federal University of Rio Grande do Sul and was Coordinator of the Postgraduate Program in Microelectronics (PGMICRO) for 4 years and she was Head of the Department of Applied Informatics for 2 years. She is currently the Administrative Director of the Brazilian Society of Microelectronics (SBMICRO). She has experience in the area of Microelectronics and Computer Engineering, with an emphasis on Hardware, working mainly on the following topics: radiation fault protection techniques, fault-tolerant system design, programmable architecture, FPGA, qualification of systems and integrated circuits under faults and fault modeling. She is the author of the book Fault Tolerance Techniques for SRAM-based FPGAs published in 2006 by Springer and co-author of 3 other scientific books. She participated in the project of the payload of the NanoSat-BR1 satellite that was launched in June 2014 and NanoSat-BR2 where part of the payload is responsible for analyzing the effects of SAA on Integrated Circuits manufactured in nanometric technology launched in 2021.