Hardware Acceleration for Post-Quantum Cryptography: Algorithmic Derivation and Architectural Innovation
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Title: Hardware Acceleration for Post-Quantum Cryptography: Algorithmic Derivation and Architectural Innovation
Speaker: Dr. Jiafeng (Harvest) Xie, Associate Professor
Department of Electrical and Computer Engineering, Villanova University
Date and Time: Monday, July 27, 2026, 1:30-2:30 PM
Location: George Mason University, ENGR 3507, 4511 Patriot Cir, Fairfax, VA 22030
Abstract: Post-quantum cryptography (PQC) has drawn significant attention from various communities recently, as the existing public-key cryptosystems, such as Rivest Shamir Adleman (RSA) and Elliptic Curve Cryptography (ECC), are proven to be vulnerable to large-scale quantum computers executing Shor’s algorithm. The National Institute of Standards and Technology (NIST) has already begun the PQC standardization process, and hardware acceleration for PQC algorithms is one of the most recent areas of focus. In this talk, I will follow this trend by introducing several interesting methods to accelerate PQC algorithms on the hardware platform. Specifically, this talk will present hardware implementation methods from both algorithmic derivation and architectural innovation perspectives. Implementation techniques for specific NIST-selected PQC schemes are also covered in this talk. I hope this talk will facilitate additional research to support PQC standardization and further development.
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- George Mason University,
- 4511 Patriot Cir, Fairfax, VA 22030
- Fairfax, Virginia
- United States 22030
- Building: Engineering Building
- Room Number: ENGR 3507
Speakers
Topic:
Hardware Acceleration for Post-Quantum Cryptography: Algorithmic Derivation and Architectural Innovation
Dr. Jiafeng (Harvest) Xie, Associate Professor
Department of Electrical and Computer Engineering, Villanova University
Biography:
Speaker: Dr. Xie is currently an Associate Professor in the Department of Electrical and Computer Engineering at Villanova University. His research interests include post-quantum security and computing, cryptographic engineering, hardware security, and digital design for large-scale computing systems. Dr. Xie has served as a technical committee member for several reputable conferences, including HOST, ICCAD, and DAC. He is also currently serving as Associate Editor for IEEE T-SP and ACM TRETS. He is also serving as the Senior Associate Editor for IEEE Transactions on Circuits and Systems-II: Express Briefs. He received the IEEE Access Outstanding Associate Editor Award for 2019. He also received the 2022 IEEE Philadelphia Section Merrill Buckley Jr. Student Project Award, the Best Paper Award from the IEEE International Symposium on Hardware Oriented Security and Trust 2019 (HOST'19), and the IEEE Philadelphia Section Engineer of the Year Award 2024. He is currently the Secretary for the IEEE Philadelphia Section.
Contact: Dr. Jiafeng (Harvest) Xie (jiafeng.xie@villanova.edu)