Vertical Power Delivery for AI Data Centers: Integrated Inductive and Capacitive Voltage Regulation and Point-of-Load Converters
The rapid growth of AI and accelerated computing is driving unprecedented demands on power delivery systems, including higher processor currents, faster load transients, tighter voltage regulation, and increasing power density at the package and board levels. This talk focuses on vertical power delivery architectures, with particular emphasis on point-of-load (PoL) converters, including emerging integrated voltage regulator (IVR) and Continuous-capacitive voltage regulator (C2VR) approaches.
The session will examine how IBCs and PoL converters can be architected and coordinated to efficiently deliver power from the rack and board level to high-current processors such as GPUs and TPUs. Different converter approaches—including inductive, resonant, and continuous-capacitor topologies—will be discussed in terms of efficiency, power density, transient response, voltage regulation, thermal performance, scalability, and reliability. Particular attention will be given to vertical integration of power conversion within packages, substrates, and near-chip environments, where reduced power-delivery impedance and shorter electrical paths can enable significant improvements in dynamic performance.
The webinar will highlight the tradeoffs between IBCs and near-load regulation, and discuss how IVR and capacitive VR technologies can complement conventional PoL architectures to address the extreme current density and fast dynamic requirements of next-generation AI processors. The discussion will provide a system-level perspective on emerging vertical power delivery architectures and the design considerations needed to achieve efficient, high-density, and highly responsive power delivery for future accelerated computing platforms.
Date and Time
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- 1111 Engineering Drive
- Boulder, Colorado
- United States 80309
- Building: 422 UCB
- Room Number: ECEE 1B32
- Starts 31 August 2026 06:00 AM UTC
- Ends 09 September 2026 11:00 PM UTC
- No Admission Charge
Speakers
Kishan Joshi
Vertical Power Delivery for AI Data Centers
The rapid growth of AI and accelerated computing is driving unprecedented demands on power delivery systems, including higher processor currents, faster load transients, tighter voltage regulation, and increasing power density at the package and board levels. This talk focuses on vertical power delivery architectures, with particular emphasis on point-of-load (PoL) converters, including emerging integrated voltage regulator (IVR) and Continuous-capacitive voltage regulator (C2VR) approaches.
The session will examine how IBCs and PoL converters can be architected and coordinated to efficiently deliver power from the rack and board level to high-current processors such as GPUs and TPUs. Different converter approaches—including inductive, resonant, and continuous-capacitor topologies—will be discussed in terms of efficiency, power density, transient response, voltage regulation, thermal performance, scalability, and reliability. Particular attention will be given to vertical integration of power conversion within packages, substrates, and near-chip environments, where reduced power-delivery impedance and shorter electrical paths can enable significant improvements in dynamic performance.
The webinar will highlight the tradeoffs between IBCs and near-load regulation, and discuss how IVR and capacitive VR technologies can complement conventional PoL architectures to address the extreme current density and fast dynamic requirements of next-generation AI processors. The discussion will provide a system-level perspective on emerging vertical power delivery architectures and the design considerations needed to achieve efficient, high-density, and highly responsive power delivery for future accelerated computing platforms.
Biography:
Dr. Kishan Joshi received his M.S. & Ph.D. degrees in electrical engineering from Arizona State University, Tempe, AZ, USA in 2016 & 2020 and his B.E in Electronics & Communication from B.V.B. College of Engineering & Technology, Hubli, India. He is currently working as an Analog Engineering Manager at Intel Corp., Santa Clara, CA on fully integrated voltage regulators. Prior to joining Intel, Kishan has worked at Texas Instruments Inc. Tucson, AZ in the Linear Power group designing Low DropOut regulators from 2019 to 2021. From 2012 to 2014 he was a Digital Circuit Designer at Sankalp Semiconductors Pvt. Ltd., India where he worked on standard cell library design for mixed-signal libraries. His current research interests include integrated vertical power delivery, low-power analog design, supply ripple rejection and power management IC design. He is an Associate Editor at Transactions on Power Electronics as well as a peer reviewer for IEEE Access, TCAS-I & II, SSCL, APEC, ISCAS. He is also the Vice-Chair of IEEE Santa Clara Valley Section for 2025 & 2026. From 2022-2024 he has been serving as the Chair of San Francisco Bay Area Council PELS Chapter. He is currently serving as the Regional Chair for IEEE PELS Region 4-6 overseeing ~40 chapters. He is also a member of the PELS TC-10 on design methodologies and PELS TC-2 on Power Components, Integration and Power ICs. Kishan has served as the Electronic Media Co-Chair for ECCE 2025, Tutorials Committee Co-Chair for ECCE 2026, Track Chair for APEC 2026 in the DC-DC Converter Track.
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