IEEE SSCS Oregon Chapter October Meeting and Seminar (Virtual)
IEEE SSCS Oregon Chapter October Meeting and Seminar
Join us for a talk from SSCS Distinguished Lecturer Prof. Jae-sun Seo from Cornell Tech on Friday, October, 2nd, 2026. The seminar will be held from 1:00pm to 2:00pm (PDT) via a Virtual format. Please register for the meeting link and information.
Topic:
Recent Digital Compute-In-Memory Designs with Various Precision/Sparsity Schemes and SoC-level Evaluation
Abstract:
This talk will present the recent landscape of digital compute-in-memory (CIM) designs for AI applications from my research group and the literature. It will feature digital CIM macro chip designs with sparse computing using compressed weights, low-to-high precision support, and different number formats including integer, floating-point, and microscaling. While high energy-efficiencies have been reported at the CIM macro levels, it is important to evaluate the energy-efficiency of CIM based accelerators at the system-on-chip (SoC) level for practical system considerations. We present collective benchmarking framework development efforts for 2D SoC and 3D IC designs, showcasing the benefits and considerations of CIM designs at the system level.
Speaker Biography:
Jae-sun Seo is an Associate Professor at the ECE department at Cornell Tech since July 2023, before which he was an Associate/Assistant Professor at Arizona State University since 2014. He was a visiting researcher at Meta Reality Labs from 2022 to 2023, and he worked at IBM T. J. Watson Research Center from 2010 to 2013.
His research interests include efficient ASIC and FPGA hardware design of machine learning algorithms and neuromorphic computing. Dr. Seo was a recipient of the 2012 IBM Outstanding Technical Achievement Award, 2017 NSF CAREER Award, 2020 Intel Outstanding Researcher Award, and 2022 IEEE TVLSI Best Paper Award. He has served on the technical program committees for ISSCC, ESSERC, ISCA, HPCA, MLSys, DAC, DATE, etc.
Date and Time
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- Starts 09 September 2026 06:00 PM UTC
- Ends 02 October 2026 07:00 PM UTC
- No Admission Charge
Speakers
Prof. Jae-sun Seo of Cornell Tech
Recent Digital Compute-In-Memory Designs with Various Precision/Sparsity Schemes and SoC-level Evaluation
This talk will present the recent landscape of digital compute-in-memory (CIM) designs for AI applications from my research group and the literature. It will feature digital CIM macro chip designs with sparse computing using compressed weights, low-to-high precision support, and different number formats including integer, floating-point, and microscaling. While high energy-efficiencies have been reported at the CIM macro levels, it is important to evaluate the energy-efficiency of CIM based accelerators at the system-on-chip (SoC) level for practical system considerations. We present collective benchmarking framework development efforts for 2D SoC and 3D IC designs, showcasing the benefits and considerations of CIM designs at the system level.
Biography:
Jae-sun Seo is an Associate Professor at the ECE department at Cornell Tech since July 2023, before which he was an Associate/Assistant Professor at Arizona State University since 2014. He was a visiting researcher at Meta Reality Labs from 2022 to 2023, and he worked at IBM T. J. Watson Research Center from 2010 to 2013.
His research interests include efficient ASIC and FPGA hardware design of machine learning algorithms and neuromorphic computing. Dr. Seo was a recipient of the 2012 IBM Outstanding Technical Achievement Award, 2017 NSF CAREER Award, 2020 Intel Outstanding Researcher Award, and 2022 IEEE TVLSI Best Paper Award. He has served on the technical program committees for ISSCC, ESSERC, ISCA, HPCA, MLSys, DAC, DATE, etc.
Agenda
1:00pm - 2:00pm: Professional/Career Seminar