The Road to Gate-All-Around CMOS

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IEEE Solid-State Circuits Society — Boise Chapter
Distinguished Lecture Series

The IEEE Solid-State Circuits Society (SSCS) — Boise Chapter cordially invites you to an upcoming Lecture presented by Dr. Alvin Loke.

Abstract

Despite the much-debated end of Moore’s Law, CMOS scaling still maintains economic relevance — with 2nm gate-all-around SoCs (Intel 18A) already in high-volume manufacturing since January 2026. Area scaling extensively driven by design/technology innovations co-optimized for logic scaling continues to offer compelling node-to-node power, performance, area, and cost benefits.

In this tutorial, we will start with a walk through memory lane, recounting a brief history of transistor evolution to motivate the migration from the planar MOSFET to the fully depleted FinFET. We will summarize the key process technology elements that have enabled FinFET CMOS nodes, highlighting the resulting technology characteristics and challenges. This will set the stage for transitioning to the nanoribbon gate-all-around device architecture and unveiling the magic of how these devices are fabricated.


  Date and Time

  Location

  Hosts

  Registration


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  • Boise State University
  • Boise, Idaho
  • United States
  • Building: MCMR
  • Room Number: 105
  • Contact Event Hosts
  • Co-sponsored by IEEE Boise Section
  • Starts 17 September 2026 06:00 AM UTC
  • Ends 30 September 2026 06:00 AM UTC
  • No Admission Charge

  Speakers

Topic:

Dr. Alvin Loke - SSCS Distinguished Lecturer

Biography:

Dr. Alvin Loke is a Senior Principal Engineer at Intel, San Diego, working on analog design/technology co-optimization for Intel's gate-all-around CMOS. He has previously worked on CMOS nodes spanning 250nm to 2nm at Agilent, AMD, Qualcomm, TSMC, and NXP.

Alvin received a BASc from the University of British Columbia, and an MS and PhD from Stanford University. After several years in CMOS process integration, he has focused on analog/mixed-signal design, including chiplet IOs, design/model/technology interface, and analog design methodologies.

Alvin has been an active IEEE Solid-State Circuits Society (SSCS) volunteer since 2003, having served as AdCom Member, CICC Committee Member, Webinar Chair, and Denver and San Diego Chapter Chair, as well as Guest Editor for JSSC, SSCL, and Solid-State Circuits Magazine. He currently serves as VLSI Symposium Secretary, SSCS Global Chapters Chair, and SSCS Distinguished Lecturer.

Alvin frequently speaks on CMOS technology and its impact on analog design. His invited works include the CICC 2018 Best Paper and short courses at ISSCC, VLSI Symposium, CICC, and BCICTS.




Agenda

Event Details

Title: The Road to Gate-All-Around CMOS
Speaker: Dr. Alvin Loke, Senior Principal Engineer, Intel
Date: Wednesday, September 30th
Time: 6:00 PM – 7:00 PM
Location: Boise State University, Room MCMR 105
Free & Open to All


We look forward to seeing you there!
IEEE SSCS — Boise Chapter thollis@ieee.org