Co-Packaged Optics with Silicon Photonics for Chiplets Heterogeneous Integration

#Co-packaged #Optics #Photonics #electronics-packaging #Advanced-Packaging #technology #Codesign #Processing
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Co-packaged optics (CPO) are heterogeneous integration packaging methods to integrate the optical engine (OE) which consists of photonic ICs (PIC) such as the laser and photodiodes, and the electrical engine (EE) which consists of the electronic ICs (EIC) such as the laser driver and transimpedance amplifiers (TiA). The advantages of CPO are: (a) to reduce the length of the electrical interface between the OE/EE (or PIC/EIC) and the ASIC, (b) to reduce the energy required to drive the signal, and (c) to cut the latency which leads to better electrical performance. In the next few years, we will see more implementations of a higher level of heterogeneous integration of EIC and PIC with silicon photonics, whether it is for performance, form factor, power consumption or cost. The content of this lecture is shown below.

                  • Introduction
                  • Data Centers
                  • Optical Transceivers
                  • PIC and EIC
                  • OBO (on-board optics), NPO (near-board optics), CPO (co-packaged optics)
                  • 3D Integration of the PIC and EIC
                  • 3D Heterogeneous Integration of ASIC Switch, PIC and EIC
                  • 3D Heterogeneous Integration of ASIC Switch, PIC and EIC with Bridges
                  • 3D Heterogeneous Integration of ASIC Switch, EIC and PIC with Glass Packaging
                  • CPO with Silicon Photonics
                  • Summary and Recommendations

The schedule is as follows: 

4-4.30 pm - Networking

4.30-6 pm - Lecture


  Date and Time

  Location

  Hosts

  Registration


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  • 6455 Lusk Blvd
  • San Diego, California
  • United States 92121
  • Building: Qualcomm Building Q Auditorium
  • Contact Event Host
  • Starts 26 September 2026 07:00 AM UTC
  • Ends 10 November 2026 11:00 PM UTC
  • No Admission Charge

  Speakers

John Lau

Biography:

John H Lau, with more than 40 years of R&D and manufacturing experience in semiconductor packaging, has published more than 530 peer-reviewed papers (385 are the principal investigator), 52 issued and pending US patents (31 are the principal inventor), and 23 textbooks. John is an elected IEEE fellow, IMAPS Fellow, and ASME Fellow and has been actively participating in industry/academy/society meetings/conferences to contribute, learn, and share. 




Agenda

4-4.30 pm - Networking

4.30-6 pm - Lecture